FEMs

• State machine for ROC/FEM communication:

  • Builds event header/trailer words.
  • Cycles through ROCs, copying data into DCM FIFO:
    • 96 data bits per ROC
    • Plus 16 bit beam clock counter to identify I/O errors
  • FPGA implementation, simulated.

• State machine for T&C communication (mode control):

  • FPGA implementation, simulated.

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