FEM Block Diagram

/HALT

Arc Addr/Data

Mode CLK

Xfer Mode (2)

MP_dat (2)

5

GLink

To DCM

GLink

XMIT

FIFO

Arcnet

Subsystem

LVL1accept

BCLK

4xBCLK

ENDAT0

UserBit[2:0]

ModeBits[7:0]

Mode Enable

GLink

RCV

GLink

From T&C

P3 Backplane

FPGA

Mode Bits (20)

Resets (4)

Align bit

ROC Data

FEM Addr

16

5

/ALE

/ROC_DV

Geographic

Address (6)

Data (16)

Data

Formatter

Strobe, /CAV, /Dav

Data

(16)

Mode Control

Address & RD Cntrl (7)

Front Panel

Serial Data (6)

Address

Decode

PLD

Command

Lines (7)

FPGA

Program (6)

Tx Reset,

Locked,

ED

Rx Reset,

Stat0

Data Formatter

Diagnostic

FPGA

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