ROC Block Diagram

Trigger

GLink

(60 MHz)

P2

{

P3

analog data

Backplane

BCLK

Board Resets (4)

/RD

LVL1_Acpt

Align bit

sdin,

rdback,

slatch,

sclk,

sdout,

sreset

TTL GLink

Circuit

Mode CLK

FEM Device Addr (5)

Arcnet Addr/Data (5)

Address

Decode

PLD

Align bit

Trigger Data

6X BCLK

Geographic Address (6)

6

Receiver

&

Threshold

Delay &

Latch

FPGAs (6)

and

Clock

delay

chips (12)

Data

Store

FIFOs

(3)

Trigger

Format

FPGA

Data

16

LVL1_Acpt

/DV

Data (16)

BCLK

Five

Event

FIFO

FPGA

Serial

String &

Pulser

28

/HALT

FPGA Prog.

/RD

/RD_EN

/DV

/RD_EN

5

Analog

Muxes (7)

Analog Spy

Output

Digital Spy

Output

96

Pulser

lines

96

FIFO cntrl

6

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