Read-Out Card

Trigger

Glink

(60 MHz)

P2

{

P3

analog data

Backplane

FD

BCLK

DMU Rst

RD_EN

LVL1_ACPT

DMU OUT0

DMU OUT1

Align bit

FD

FD

FD

FD

FD

SDIN,

Readback,

D_LATCH,

SCLK,

SDOUT,

Ser Rst,

DMU

DMU

Glink

Circuit

Device Addr (6)

Addr Latch

SDIN/ED

SDOUT/Locked

Address

Decode

PLD

Locked

Align bit

Trigger

Format

FPGA

BCLK

Trigger Data

6X BCLK

16

16

16

16

20

6

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