Summary
The design of the TGID ASIC is based on many existing blocks.
The chip will read 16 channels of data from the Iarocci tube pre-amplifiers.
Output will be to the PADS DMU and to the LVL1 Trigger G-link FPGA.
The chip will have a receiver, discriminator, variable delay, test pulser, serial interface, DACs and multiplexer outputs.
Preliminary designs are underway.