Development Milestones

• 9/15 Layout and simulate DACs

• 9/30 Layout and simulate receiver/pulser

• 9/30 Layout and simulate discriminator

• 9/30 Layout and simulate variable delay

• 10/15 Assemble single channel and simulate

• 10/30 Assemble core and simulate

• 11/15 Pad route

• 12/1 Final chip layout and simulation

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