The scheme described on the previous slide has to be developed in order to read out the MVD on-board voltages. Other subsystems may want to join the project. It makes no sense for a subsystem with few ancillary readout channels, since there is the startup cost of the I/O module.
Subsystems that are interested should speak up soon, so that we can make sure that their concerns get addressed in the design of the board. In particular, the things I've heard about (from TC) include: