Finding front end electronics problems

1. Turn off HV
2. Take a pedestal run with GTM file GTM.pbgl_init_shortlong_IY.gtm It allows to have all AMU cells occupied
3. Run ped prdffile.prdf where prdffile.prdf is the name of file with the full path. It is ussulay stored in $STANDALONE_DISK/calibdata/ or $STANDALONE_DISK/junkdata/
4. Start root -l show.C. To proceed with the next couple of plots double click on canvas with the name *E0
5. Interpret plots. Each small square represents 2x2 modules set. Large square outlined with bold lines represents one FEM. Each plot show different types of problems:

   Dead Channels	Circuit in Mondo chip corresponding to this channel is short-ciruited. No data can be recieved from this channel. ASIC board should be swappped out
   Bad sigma pre post	One of hg_pre, hg_post, lg_pre, lg_post signals has large RMS. This plot is made just for notification as noise in any of this signals means nothing by itself.
   Ped high LG RMS	Low gain pre-post signal is noisy. With HV off RMS more than 5 is considered to be bad and RMS more that 10 is considered to be very bad (average value is 2-3 channels)
   Ped high HG RMS	High gain pre-post signal is noisy. With HV off RMS more than 5 is considered to be bad and RMS more that 10 is considered to be very bad and if RMS more that 15 for the whole ASIC this board is considered to be useless (average value is 2-3 channels)
   Ped bad TAC values	TAC pedestal values can not be improved by adjusting serial string parameters. Therefore ASIC considered bad should be swapped out
   Ped high TAC RMS	TAC signal is noisy. RMS more than 7 is considered to be bad and RMS more that 15 is considered to be very bad (average value is about 5 channels)
   Bad LG or HG values	In this case "bad" means very high. Modules having their pre or post pedestals at 4095 are marked as "dead" and having their pedestals at more than 4000 are marked as "too high LG/HG". These modules serial strings should be adjusted usind sdata.

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   Last update:
   Andrey Kazantsev