ROCs: Analog Processing Chain - Variable Delay - cont.
Maximum gate width reduced to 90 ns by set/hold requirements.
Further reduced to 80 ns by convolution with transmission time down length of LST.
Failure to match T0 leads to 1% efficiency loss every 3 ns.
Inefficiency vs. gate width for different isobutane/CO2 ratios. Measurement is for a 2-pack at one longitudinal location.