Why a TGID ASIC FEE?
ASIC can provide much lower per channel power, higher ROC channel density and lower per channel cost
Early ASIC design, ie. pinouts, enhances schedule by allowing early design of ROC, transition cards, FEM, backplane and Crate
high ROC channel density needed to reduce number of required LVL1 trigger G-Links
high ROC channel density needed to prevent complex ROC to ROC and Rack to Rack interfaces
MUID design can be coordinated with similar ASICs TGLD, MTA
no “COTS” part available that satisfies all the functional requirements for MUID readout
ROCs could be built from a combination of cots parts and discrete components
cots/discrete based designs would be at least 5 to 10 times larger with higher power per channel