Changes between 3.0 and 3.1

Changes marked with '*' are backward incompatible

# State Address Name Note Field Bits Type Description Value
1* Changed 0x0050 NUM_OF_CHANNELS 7..0 R Number of GBT Channels std_logic_vector(to_unsigned(GBT_NUM,8))
1* Into 0x0050 NUM_OF_CHANNELS 7..0 R Number of GBT Channels None
2* Changed 0x0070 GBT_MAPPING 7..0 R CXP-to-GBT mapping:
0: NORMAL CXP1 1-12 CXP2 13-24
1: ALTERNATE CXP1 1-4,9-12,17-20
std_logic_vector(to_unsigned(GBT_MAPPING,8))
2* Into 0x0070 GBT_MAPPING 7..0 R CXP-to-GBT mapping:
0: NORMAL CXP1 1-12 CXP2 13-24
1: ALTERNATE CXP1 1-4,9-12,17-20
None
3 Added 0x0080 GENERATE_GBT 0 R 1 when the GBT Wrapper is included in the design None
4 Added 0x0090 OPTO_TRX_NUM 7..0 R Number of optical transceivers in the design None
5 Added 0x00A0 TTC_EMU_CONST
Added GENERATE_TTC_EMU 1 R 1 when TTC emulator is generated None
Added TTC_TEST_MODE 0 R 1 when TTC Test mode is anabled None
6 Added 0x00B0 CR_INTERNAL_LOOPBACK_MODE 0 R 1 when Central Router internal loopback mode is enabled None
7 Added 0x00C0 INCLUDE_EPROC16 0 R EPROC16 is included in Central Router None
8 Added 0x00D0 WIDE_MODE 0 R GBT is configured in Wide mode None
9 Added 0x00E0 DEBUG_MODE 0 R 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
None
10 Changed 0x7300 MMCM_MAIN
Changed OSC_SEL 1 R Main MMCM Oscillator Select None
PLL_LOCK 0 R Main MMCM PLL Lock Status None
10 Into 0x7300 MMCM_MAIN
Added AUTOMATIC_CLOCK_SWITCH_ENABLED 2 R 1 when the automatic clock switch is enabled in the design None
Into OSC_SEL 1 R Main MMCM Oscillator Select
1: TTC clock
0: Local clock
None
PLL_LOCK 0 R Main MMCM PLL Lock Status None