| # | State | Address | Name | Note | Field | Bits | Type | Description | Value |
|---|---|---|---|---|---|---|---|---|---|
| 1* | Removed | 0x0000 | BOARD_ID | ||||||
| Removed | SVN | 79..64 | R | Board ID SVN Revision | std_logic_vector(to_unsigned(SVN_VERSION,16)) | ||||
| Removed | TIMESTAMP | 39..0 | R | Board ID Date / Time in BCD format YYMMDDhhmm | BUILD_DATETIME | ||||
| 2 | Added | 0x0000 | BOARD_ID_TIMESTAMP | 39..0 | R | Board ID Date / Time in BCD format YYMMDDhhmm | BUILD_DATETIME | ||
| 3 | Added | 0x0008 | BOARD_ID_SVN | 15..0 | R | Board ID SVN Revision | std_logic_vector(to_unsigned(SVN_VERSION,16)) | ||
| 4* | Changed | 0x4010 | GBT_EMU_CONFIG | ||||||
| Removed | WE_ARRAY | 70..64 | W | write enable array, every bit is one emulator RAM block | None | ||||
| WRADDR | 45..32 | W | write address bus | None | |||||
| WRDATA | 15..0 | W | write data bus | None | |||||
| 4* | Into | 0x4010 | GBT_EMU_CONFIG | ||||||
| WRADDR | 45..32 | W | write address bus | None | |||||
| WRDATA | 15..0 | W | write data bus | None | |||||
| 5 | Added | 0x4018 | GBT_EMU_CONFIG_WE_ARRAY | 6..0 | W | write enable array, every bit is one emulator RAM block | None | ||
| 6* | Removed | 0x7200 | HK_CTRL | ||||||
| Removed | CDCE_REF_SEL | 66 | W | REF_SEL | None | ||||
| Removed | CDCE_PD | 65 | W | PD | None | ||||
| Removed | CDCE_SYNC | 64 | W | SYNC | None | ||||
| Removed | I2C_CONFIG_TRIG | 1 | W | i2c_config_trig | None | ||||
| Removed | I2C_CLKFREQ_SEL | 0 | W | i2c_clkfreq_sel | None | ||||
| 7 | Added | 0x7200 | HK_CTRL_I2C | ||||||
| Added | CONFIG_TRIG | 1 | W | i2c_config_trig | None | ||||
| Added | CLKFREQ_SEL | 0 | W | i2c_clkfreq_sel | None | ||||
| 8 | Added | 0x7208 | HK_CTRL_CDCE | ||||||
| Added | REF_SEL | 2 | W | REF_SEL | None | ||||
| Added | PD | 1 | W | PD | None | ||||
| Added | SYNC | 0 | W | SYNC | None | ||||
| 9* | Removed | 0x7500 | DEBUG_PORT | ||||||
| Removed | CLK | 67..64 | W | Debug clock and L1A port on SMA HTGx#4 | None | ||||
| Removed | GBT | 6..0 | W | Debug GBT data bit N (119..0) on SMA HTGx#3 | None | ||||
| 10 | Added | 0x7500 | DEBUG_PORT_GBT | 6..0 | W | Debug GBT data bit N (119..0) on SMA HTGx#3 | None | ||
| 11 | Added | 0x7508 | DEBUG_PORT_CLK | 3..0 | W | Debug clock and L1A port on SMA HTGx#4 | None | ||