| Address | Name | Field | Bits | Type | Description |
|---|---|---|---|---|---|
| Bar2 | |||||
| Generic Board Information | |||||
| 0x0000 | BOARD_ID | SVN | 79..64 | R | Board ID SVN Revision |
| TIMESTAMP | 39..0 | R | Board ID Date / Time in BCD format YYMMDDhhmm | ||
| 0x0010 | STATUS_LEDS | 7..0 | W | Board GPIO Leds | |
| 0x0020 | GENERIC_CONSTANTS | INTERRUPTS | 15..8 | R | Number of Interrupts |
| DESCRIPTORS | 7..0 | R | Number of Descriptors | ||
| 0x0030 | NUM_OF_CHANNELS | 7..0 | R | Number of GBT Channels | |
| 0x0040 | CARD_TYPE | 63..0 | R | Card Type: - 709: VC709 - 710: HTG710 |
|
| 0x0050 | GBT_MAPPING | 7..0 | R | CXP-to-GBT mapping: 0: NORMAL CXP1 1-12 CXP2 13-24 1: ALTERNATE CXP1 1-4,9-12,17-20 |
|
| Central Router Controls | |||||
| GBT_CONTROL | |||||
| TH | |||||
| 0x1100 | CR_TH_GBT00_EGROUP0_CTRL | 63..0 | W | See Central Router Doc, indices [5,6] are optimized out in wideMode | |
| ... | |||||
| 0x1160 | CR_TH_GBT00_EGROUP6_CTRL | 63..0 | W | See Central Router Doc, indices [5,6] are optimized out in wideMode | |
| FH | |||||
| 0x1170 | CR_FH_GBT00_EGROUP0_CTRL | 63..0 | W | See Central Router Doc, indices [3,4] are optimized out in wideMode | |
| ... | |||||
| 0x11B0 | CR_FH_GBT00_EGROUP4_CTRL | 63..0 | W | See Central Router Doc, indices [3,4] are optimized out in wideMode | |
| ... | |||||
| TH | |||||
| 0x2240 | CR_TH_GBT23_EGROUP0_CTRL | 63..0 | W | See Central Router Doc, indices [5,6] are optimized out in wideMode | |
| ... | |||||
| 0x22A0 | CR_TH_GBT23_EGROUP6_CTRL | 63..0 | W | See Central Router Doc, indices [5,6] are optimized out in wideMode | |
| FH | |||||
| 0x22B0 | CR_FH_GBT23_EGROUP0_CTRL | 63..0 | W | See Central Router Doc, indices [3,4] are optimized out in wideMode | |
| ... | |||||
| 0x22F0 | CR_FH_GBT23_EGROUP4_CTRL | 63..0 | W | See Central Router Doc, indices [3,4] are optimized out in wideMode | |
| 0x2300 | CR_TH_UPDATE_CTRL | any | T | See Central Router Doc | |
| 0x2310 | CR_FH_UPDATE_CTRL | any | T | See Central Router Doc | |
| Central Router Monitors | |||||
| GBT_MON | |||||
| 0x3000 | CR_TH_GBT00_MON | 63..0 | R | See Central Router Doc | |
| 0x3010 | CR_FH_GBT00_MON | 63..0 | R | See Central Router Doc | |
| ... | |||||
| 0x32E0 | CR_TH_GBT23_MON | 63..0 | R | See Central Router Doc | |
| 0x32F0 | CR_FH_GBT23_MON | 63..0 | R | See Central Router Doc | |
| GBT Emulator Controls And Monitors | |||||
| 0x4000 | GBT_EMU_ENA | TOHOST | 1 | W | Enable GBT dummy emulator ToHost |
| TOFRONTEND | 0 | W | Enable GBT dummy emulator ToFrontEnd | ||
| 0x4010 | GBT_EMU_CONFIG | WE_ARRAY | 70..64 | W | write enable array, every bit is one emulator RAM block |
| WRADDR | 45..32 | W | write address bus | ||
| WRDATA | 15..0 | W | write data bus | ||
| GBT Wrapper Controls | |||||
| 0x5400 | GBT_LOGIC_RESET | 63..0 | W | Not internally connected (?) | |
| 0x5410 | GBT_GENERAL_CTRL | 63..0 | W | Alignment chk reset (not self clearing) | |
| 0x5420 | GBT_MODE_CTRL | RX_ALIGN_TB_SW | 2 | W | RX_ALIGN_TB_SW |
| RX_ALIGN_SW | 1 | W | RX_ALIGN_SW | ||
| DESMUX_USE_SW | 0 | W | DESMUX_USE_SW | ||
| 0x5480 | GBT_RXSLIDE | BF1 | 59..48 | W | RxSlide select [23:12] |
| BF2 | 43..32 | W | RxSlide select [11:0] | ||
| BF3 | 27..16 | W | RxSlide manual [23:12 | ||
| BF4 | 11..0 | W | RxSlide manual [11:0] | ||
| 0x5490 | GBT_TXUSRRDY | BF1 | 27..16 | W | TxUsrRdy [23:12] |
| BF2 | 11..0 | W | TxUsrRdy [11:0] | ||
| 0x54A0 | GBT_RXUSRRDY | BF1 | 27..16 | W | RxUsrRdy [23:12] |
| BF2 | 11..0 | W | RxUsrRdy [11:0] | ||
| 0x54B0 | GBT_GTTX_RESET | BF1 | 30..28 | W | SOFT_RESET [5:3] |
| BF2 | 27..16 | W | GTTX_RESET [23:12] | ||
| BF3 | 14..12 | W | SOFT_RESET [2:0] | ||
| BF4 | 11..0 | W | GTTX_RESET [11:0] | ||
| 0x54C0 | GBT_GTRX_RESET | BF1 | 27..16 | W | GTRX_RESET [23:0] |
| BF2 | 11..0 | W | GTRX_RESET [11:0] | ||
| 0x54D0 | GBT_PLL_RESET | BF1 | 30..28 | W | QPLL_RESET [5:3] |
| BF2 | 27..16 | W | CPLL_RESET [23:12] | ||
| BF3 | 14..12 | W | QPLL_RESET [2:0] | ||
| BF4 | 11..0 | W | CPLL_RESET [11:0] | ||
| 0x54E0 | GBT_SOFT_TX_RESET | BF1 | 30..28 | W | SOFT_TX_RESET_ALL [5:3] |
| BF2 | 27..16 | W | SOFT_TX_RESET_GT [23:12] | ||
| BF3 | 14..12 | W | SOFT_TX_RESET_ALL [2:0] | ||
| BF4 | 11..0 | W | SOFT_TX_RESET_GT [11:0] | ||
| 0x54F0 | GBT_SOFT_RX_RESET | BF1 | 30..28 | W | SOFT_RX_RESET_ALL [5:3] |
| BF2 | 27..16 | W | SOFT_RX_RESET_GT [23:12] | ||
| BF3 | 14..12 | W | SOFT_RX_RESET_ALL [2:0] | ||
| BF4 | 11..0 | W | SOFT_RX_RESET_GT [11:0] | ||
| 0x5500 | GBT_ODD_EVEN | BF1 | 27..16 | W | OddEven [23:12] |
| BF2 | 11..0 | W | OddEven [11:0] | ||
| 0x5510 | GBT_TOPBOT | BF1 | 27..16 | W | TopBot [23:12] |
| BF2 | 11..0 | W | TopBot [11:0] | ||
| 0x5520 | GBT_TX_TC_DLY_VALUE1 | 47..0 | W | TX_TC_DLY_VALUE [47:0] | |
| 0x5530 | GBT_TX_TC_DLY_VALUE2 | 47..0 | W | TX_TC_DLY_VALUE [95:48] | |
| 0x5540 | GBT_TX_OPT | 47..0 | W | TX_OPT | |
| 0x5550 | GBT_RX_OPT | 47..0 | W | RX_OPT | |
| 0x5560 | GBT_DATA_TXFORMAT | BF1 | 55..32 | W | DATA_TXFORMAT [47:24] |
| BF2 | 23..0 | W | DATA_TXFORMAT [23:0] | ||
| 0x5570 | GBT_DATA_RXFORMAT | BF1 | 55..32 | W | DATA_RXFORMAT [47:24] |
| BF2 | 23..0 | W | DATA_RXFORMAT [23:0] | ||
| 0x5580 | GBT_TX_RESET | BF1 | 27..16 | W | TX Logic reset [23:12] |
| BF2 | 11..0 | W | TX Logic reset [11:0] | ||
| 0x5590 | GBT_RX_RESET | BF1 | 27..16 | W | RX Logic reset [23:12] |
| BF2 | 11..0 | W | RX Logic reset [11:0] | ||
| 0x55A0 | GBT_TX_TC_METHOD | BF1 | 27..16 | W | TX time domain crossing method [23:12] |
| BF2 | 11..0 | W | TX time domain crossing method [11:0] | ||
| 0x55B0 | GBT_OUTMUX_SEL | BF1 | 27..16 | W | Descrambler output MUX selection [23:12] |
| BF2 | 11..0 | W | Descrambler output MUX selection [11:0] | ||
| 0x5600 | GBT_DNLNK_FO_SEL | 31..0 | W | ToHost FanOut/Selector. Every bitfield is a channel: 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel |
|
| 0x5610 | GBT_UPLNK_FO_SEL | 31..0 | W | ToFrontEnd FanOut/Selector. Every bitfield is a channel: 1 : GBT_EMU, select GBT Emulator for a specific GBT link 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link |
|
| GBT Wrapper Monitors | |||||
| 0x6600 | GBT_VERSION | DATA | 63..48 | R | Data |
| GBT_VERSION | 47..32 | R | GBT Version | ||
| GTH_IP_VERSION | 31..16 | R | GTH IP Version | ||
| RESERVED | 15..3 | R | Reserved | ||
| GTHREFCLK_SEL | 2 | R | GTHREFCLK SEL | ||
| RX_CLK_SEL | 1 | R | RX CLK SEL | ||
| PLL_SEL | 0 | R | PLL SEL | ||
| 0x6680 | GBT_TXRESET_DONE | BF1 | 27..16 | R | TX Reset done [23:12] |
| BF2 | 11..0 | R | TX Reset done [11:0] | ||
| 0x6690 | GBT_RXRESET_DONE | BF1 | 27..16 | R | RX Reset done [23:12] |
| BF2 | 11..0 | R | RX Reset done [11:0] | ||
| 0x66A0 | GBT_TXFSMRESET_DONE | BF1 | 27..16 | R | TX FSM Reset done [23:12] |
| BF2 | 11..0 | R | TX FSM Reset done [11:0] | ||
| 0x66B0 | GBT_RXFSMRESET_DONE | BF1 | 27..16 | R | RX FSM Reset done [23:12] |
| BF2 | 11..0 | R | RX FSM Reset done [11:0] | ||
| 0x66C0 | GBT_CPLL_FBCLK_LOST | BF1 | 27..16 | R | CPLL FBCLK LOST [23:12] |
| BF2 | 11..0 | R | CPLL FBCLK LOST [11:0] | ||
| 0x66D0 | GBT_CPLL_LOCK | BF1 | 30..28 | R | QPLL LOCK [5:3] |
| BF2 | 27..16 | R | CPLL LOCK [23:12] | ||
| BF3 | 14..12 | R | QPLL LOCK [2:0] | ||
| BF4 | 11..0 | R | CPLL LOCK [11:0] | ||
| 0x66E0 | GBT_RXCDR_LOCK | BF1 | 27..16 | R | RX CDR LOCK [23:12] |
| BF2 | 11..0 | R | RX CDR LOCK [11:0] | ||
| 0x66F0 | GBT_CLK_SAMPLED | BF1 | 27..16 | R | clk sampled [23:12] |
| BF2 | 11..0 | R | clk sampled [11:0] | ||
| 0x6700 | GBT_RX_IS_HEADER | BF1 | 27..16 | R | RX IS HEADER [23:12] |
| BF2 | 11..0 | R | RX IS HEADER [11:0] | ||
| 0x6710 | GBT_RX_IS_DATA | BF1 | 27..16 | R | RX IS DATA [23:12] |
| BF2 | 11..0 | R | RX IS DATA [11:0] | ||
| 0x6720 | GBT_RX_HEADER_FOUND | BF1 | 27..16 | R | RX HEADER FOUND [23:12] |
| BF2 | 11..0 | R | RX HEADER FOUND [11:0] | ||
| 0x6730 | GBT_ALIGNMENT_DONE | BF1 | 27..16 | R | RX ALIGNMENT DONE [23:12] |
| BF2 | 11..0 | R | RX ALIGNMENT DONE [11:0] | ||
| 0x6740 | GBT_OUT_MUX_STATUS | BF1 | 27..16 | R | GBT output mux status [23:12] |
| BF2 | 11..0 | R | GBT output mux status [11:0] | ||
| 0x6750 | GBT_ERROR | BF1 | 27..16 | R | Error flags [23:12] |
| BF2 | 11..0 | R | Error flags [11:0] | ||
| 0x6760 | GBT_GBT_TOPBOT_C | BF1 | 27..16 | R | TopBot_c [23:12] |
| BF2 | 11..0 | R | TopBot_c [11:0] | ||
| House Keeping Controls And Monitors | |||||
| 0x7200 | HK_CTRL | CDCE_REF_SEL | 66 | W | REF_SEL |
| CDCE_PD | 65 | W | PD | ||
| CDCE_SYNC | 64 | W | SYNC | ||
| I2C_CONFIG_TRIG | 1 | W | i2c_config_trig | ||
| I2C_CLKFREQ_SEL | 0 | W | i2c_clkfreq_sel | ||
| 0x7300 | PLL_LOCK | 1..0 | R | Main MMCM PLL Lock Status | |
| 0x7310 | HK_MON | CDCE_PLL_LOCK | 1 | R | CDCE_PLL_LOCK |
| I2C_ACK_ERROR | 0 | R | i2c_ack_error | ||
| 0x7400 | SPI_WR | SPI_WREN | any | T | Any write to this register triggers an SPI Write |
| SPI_FULL | 32 | R | SPI FIFO Full | ||
| SPI_DIN | 31..0 | W | SPI WRITE Data | ||
| 0x7410 | SPI_RD | SPI_RDEN | any | T | Any write to this register pops the last SPI data from the FIFO |
| SPI_EMPTY | 32 | R | SPI FIFO Empty | ||
| SPI_DOUT | 31..0 | R | SPI READ Data | ||
| 0x7420 | I2C_WR | I2C_WREN | any | T | Any write to this register triggers an I2C read or write sequence |
| I2C_FULL | 25 | R | I2C FIFO full | ||
| WRITE_2BYTES | 24 | W | Write two bytes | ||
| DATA_BYTE2 | 23..16 | W | Data byte 2 | ||
| DATA_BYTE1 | 15..8 | W | Data byte 1 | ||
| SLAVE_ADDRESS | 7..1 | W | Slave address | ||
| READ_NOT_WRITE | 0 | W | READ/ |
||
| 0x7430 | I2C_RD | I2C_RDEN | any | T | Any write to this register pops the last I2C data from the FIFO |
| I2C_EMPTY | 8 | R | I2C FIFO Empty | ||
| I2C_DOUT | 7..0 | R | I2C READ Data | ||
| 0x7500 | DEBUG_PORT | CLK | 67..64 | W | Debug clock and L1A port on SMA HTGx#4 |
| GBT | 6..0 | W | Debug GBT data bit N (119..0) on SMA HTGx#3 | ||
| 0x7800 | INT_TEST_2 | any | T | Fire a test MSIx interrupt #2 | |
| 0x7810 | INT_TEST_3 | any | T | Fire a test MSIx interrupt #3 | |