config top;
design alpide_pwr_extension_v1_2_lib.top:sim_sch_1;
liblist alpide_pwr_extension_v1_2_lib, standard, cnconnector, cnpassive, cnstandard, cnpower, its_chips;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
stoplist none;
endconfig
