Advanced VHDL ex06 - Vivado Simulation and Implementation

These instructions assume you are starting a new project.

  1. Set up a project as follows:
    • Start Vivado and click on Create New Project
    • Next
    • Set project location to ".../ex06/synthesize", Project Name to "ex06proj", Next
    • RTL Project, Next
    • Add Sources - add ex06/source/counter.vhd, ex06/source/counter_tb_pack.vhd, ex06/source/counter_tb.vhd. Make sure that the testbench and its package are not selected for synthesis. Next
    • Add Constraints (optional), Next
    • Click on Boards, Select the Zedboard, Next
    • Finish
  2. To run simulation
    • In the Flow Navigator, click Settings. When the dialog appears, click Simulation on the left hand side and then the Simulation tab. Enter "all" in the xsim.simulate.runtime field. Click OK.
    • In the Flow Navigator, click Run Simulation.
    • In the dialog that appears, select Run Behavioral Simulation
    • Inspect the waveforms and check that they are as expected.
  3. Next, we need to open the constraint editor:
    • In the Flow Navigator, click Run Synthesis
    • If the option appears, click Open Synthesized Design - if it doesn't appear, click Open Synthesized Design in the Flow Manager
    • Click Edit Timing Constraints (an option under Open Synthesized Design in the Flow Manager)
  4. Timing Constraints Editor opens.
    • In the left pane of the Timing Constraints tab, make sure Create Clock(0) is highlighted.
    • Double-Click on the message "Double click to create a Create Clock Constraint" in the right pane
    • Enter a name for the clock in the "Clock name" field (eg CLOCK)
    • In the Source Object:, click ... The Specify Clock Source Objects dialog appears. Click Find
    • A list of ports appears. Double click Clock in the results. This will move it into the Select Names: section.
    • Click Set to close the Specify Clock Source Objects dialog.
    • You can now edit the Waveform - but the default of 10ns is good enough, so click OK.
    • Save the constraints by Clicking File > Save Constraints (Click OK if an Out of Data Design dialog appears). Enter the name "counter" in the File name field and click OK.
    • Click OK to close the Timing Constraint editor.

Now it is possible to implement the design, and then look at the performance relative to the clock constraint you have specified.

  1. Next you can implement the design and look at the results
    • Click Run Implementation in the Flow Manager (answer Yes if asked to run Synthesis again)
    • When Place & Route has finished, the Implementation Completed dialog may appear - if it does, select View Reports, OK
    • If that option did not appear, click the Reports tab near the bottom of the screen
    • In the Reports tab, scroll down and double click Timing Summary Report (which is in the Route Design section).
      For each timing constraint, this will tell you whether the constraint was met. Look for the Timing Details section, and then the section Max Delay Paths.
  2. To obtain more detail use the Timing Analzer. To start the Timing Analyzer:
    • In the Flow Manager, click Report Timing Summary.
    • Click OK - the timing summary will appear at the bottom.

Now it is possible to simulate the gate-level model.

  1. To run the gate-level simulation
    • In the Flow Navigator, click Run Simulation.
    • In the dialog that appears, select Run Post-Implementation Timing Simulation. If a Timing Simulation dialog appears, click Yes.
    • Inspect the waveforms and observe the delay between the rising edge of clock and the transitions on the counter's Q outputs.