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This section describes synthesis use Xilinx's Vivado synthesis tool, followed by Place & Route in Vivado. If you are using a third party synthesis tool (such as Synopsys Synplify, Mentor Precision), follow those instructions instead.
If you already have a project set up, jump to Vivado Synthesis
After a while synthesis will complete and if a "Synthesis Completed" dialog appears, click Cancel. Now you can view the synthesized design, either as RTL, or mapped onto technology primitives.
The next step is Place &Route. The tool will place and route the logic on the device, using the constraints specified in the file LOGIC.xdc. LOGIC.xdc specifies the pin locations so that the switches and LEDs on the Zedboard are used as we want.
When the Generate Bitstream has completed, the Bitstream Generation Completed dialog box shows. Select View Reports, and click OK
Click here for instructions to download the design.
synplify_pro&
Xilinx Zynq XC7Z020 CLG484 -1
Done!
You can quit the tool.
To Place and Route and download the design, go to Place and Route
Now test if your downloaded design is working!
The 4 inputs are on slide/DIP switches SW0, SW1, SW2, SW3 at the bottom edge of the board. The 4 outputs are on the LEDs LD0, LD1, LD2, LD3. The pin numbers are printed on the board, so you can relate them back to the VHDL ports by looking in the LOGIC.xdc file.