Timing Constraints and Timing Analysis

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Setting Timing Constraints

Setting accurate timing constraints is an important part of the design flow. Quartus Prime includes the TimeQuest static timing analyzer, which you will use now.

  1. First setup the project to use TimeQuest
    • Start Quartus Prime and create a new project called Counter in ex07\implement\intel_BeMicro\quartus directory. Add the file counter.vhd
    • Run Analysis & Synthesis from the Tasks Window.
    • Select menu Assignments > Settings...
    • Type the SDC filename counter.sdc and click Add. (This file doesn't exist. We will create it shortly.)
    • Click Ok
  2. To create the constraints file in TimeQuest:
    • Open TimeQuest by clicking the TimeQuest Timing Anlyzer button on the toolbar (the blue clock) or by selecting TimeQuest from the Tools menu.
    • Now you must create a Timing Netlist - you can't use the Tasks pane (on the left to do this, because that requires the desing to have been fully compiled (i.e. fitted). Instead: Select menu Netlist > Create Timing Netlist...
    • In the Create Timing Netlist dialog, select Post-map as the Input netlist, and click OK
    • To enter a clock constraint, select menu Constraints > Create Clock... to open the Create Clock dialog
    • You can leave the Clock name field blank.
    • Enter a period of 10ns
    • Click the button with three dots that is to the right of the Targets field.
    • In the Name Finder, with Collection set to get_ports, and Filter: *, click on List.
    • Double-click on the name "Clock" (or click once and then click on the ">").
    • You should see Clock as the only selected name. Click OK.
    • Click Run in the Create Clock dialog
    • As we don't want to add any more constraints for this example, select menu Constraints > Write SDC File... to save the file
    • Type the name coutner.sdc as the File name (this is the name you entered earlier, don't use the default name of counter.out.sdc)
    • Exit TimeQuest
  3. Compile the design in the usual way. After compilation:
    • Expand the TimeQuest Timing Analyzer section of the Compilation Report

      The Clocks section summarises the clock constraints, the Fmax summary tells you the maximum frequency (this can be found inside one of the process-corner sections, eg "Slow 1200mV 85C Model", and the Setup Summary tells you whether or not the clock constraint was met. (The slack is the difference between the actual and requested periods. A negative slack value indicates that a constraint was not met.). The Datasheet Report section details input and output timing.
  4. To obtain a more detailed analysis, run TimeQuest:
    • Open TimeQuest by clicking the TimeQuest Timing Analyzer button on the toolbar.
    • Double-click on Update Timing Netlist in the Tasks pane. This also runs the Create Timing Netlist and Read SDC File tasks automatically.
    • Under Macros, double-click on Report All Core Timings
    • In the Report browser (above the Tasks pane) expand Report Timing (Core) and click on Core Clock Setup: clock
    • You should see a list of all the internal paths, showing the slowest one first. Click on the top-most slack value to select it
    • Click on it again, using the right mouse button and select Report Worst-Case Path.

This gives a detailed report on the design’s critical path.

If time permits, you can explore some of the other reports. When you have finished, exit TimeQuest.

As in earlier exercises, you can now download the design to the board using the do_BeMicro.bat script