Synthesis and Place and Route

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Microsemi/Actel Libero Synthesis and Place & Route

This section describes and Place & Route using Microsemi/Actel Libero which uses Synopsys Synplify or Mentor Precision as its synthesis tool, followed by Place & Route in Microsemi/Actel Designer.

  1. Start Libero from the Windows Start menu, or a desktop icon.
  2. Create a new project as follows:
    • Select menu Project > New Project...
    • Set the following details:
      Project Name        ex01proj
      Location            browse to ex01\implement\microsemi_A3PE_Eval_Board	
      Design Entry Type   VHDL
      
    • Click Next
    • Select Device, select the following details:
      Family:       ProASIC3
      Die:          A3P250
      Package:      208 PQFP
      Speed:        -2
      Core Voltage: 1.5
      Range:        COM
      
    • Click Next
    • Default I/O Technology:   LVTTL
      
    • Click Next
    • Add HDL Source Files
    • click "Link File". Add the file ..\..\source\logic.vhd
    • Click Next
    • Click Finish
  3. You are now ready to synthesize and optimize your design.
    • Select Project->Tool Profiles->Synthesis and click the radio button next to either "Synplify Pro" or "Precision RTL Synthesis". Click OK.
    • Right click "Synthesize" in the "Design Flow" pane and select "Run". Synthesis will run.
    • Right click "Compile" in the "Design Flow" pane and select "Run". Optimization will run.
  4. You are now ready to Place and Route your design.
    • Right click on "Create/Edit I/O Attributes", which appears under "Constrain Place and Route" in the "Design Flow" pane, and select "Run Interactively".
    • The "Designer" and "Multiview Navigator" windows appear.
  5. You must now assign the pins to match those on the board.
    • Click on "I/O Attribute Editor" under "Multiview Navigator"
    • In the "Pin Number" column, set the pin numbers to:
      IN0 68
      IN1 67
      IN2 66
      IN3 64
      OUT0 58 
      OUT1 61
      OUT2 60
      OUT3 59
      
      WARNING: Port name order may not match this list!
    • To check and save the changes: on the "File" menu, select "Commit and Check"
    • To close the "Multiview Navigator": on the "File" menu, select "Exit"
  6. Next you will run the Layout process
    • In "Designer" click the "Layout" button.
    • Accept the default layout options, click "OK"
  7. Now you are ready to generate a programming file
    • Click the "Programming File" button
    • In the form "Flashpoint - Programming File Generator - Step 1 of 1" make sure that "FPGA Array" is selected (under "Silicon Feature(s) to be programmed:") and click "Finish"

      The "Generate Programming Files" form appears.
    • Check the output filename says "LOGIC" and the output format "Programming Data Files (*.pdb)" is selected.
    • Click "Generate"
    • Close "Designer", answering Yes if you are prompted to save.

You are now ready to download the bitstream to the board!

Click here for instructions to download the design.


Downloading to the Microsemi/Actel A3PE Eval Board

You are now ready to download the bitstream to the board.

  1. Prepare the board for programming:
    • Connect the 9v power supply to the board using connector J18
    • Connect the FlashPro3 box to the board through the 10 pin connector labelled "(default)".
    • Connect the FlashPro3 box to a USB socket on your computer.
    • If you connect the USB FlashPro3 programmer for the first time, the OS needs drivers. They are located in the Libero installation directory, e.g. C:\microsemi\Libero_v11.5\Designer\Drivers
  2. Program:
    • Right click on the "Program Device" in the "Program Design" section of the "Design Flow" pane and select "Run".

Now test if your downloaded design is working!


Testing the board

The 4 inputs are on push switches SW1 - SW4

The 4 outputs are on the LEDs D1-D4. You should be able to work out which pin is connected to which LED by looking at the behaviour of the LEDs as you change the inputs!