Timing Constraints and Timing Analysis

Jump to...


Setting Timing Constraints

Setting accurate timing constraints is an important part of the design flow. You will now set up some global constraints and analyze the results.

  1. Start Libero Project Manager from the Windows Start menu, or a desktop icon.
  2. Create a new project in the ex07\implement\microsemi_A3PE_Eval_Board directory as follows:
    • Select menu Project > New Project...
    • Set the following details:
      Project Name        counter
      Location            browse to ex07\implement\microsemi_A3PE_Eval_Board	
      Design Entry Type   VHDL
      Family              ProASIC3
      Die                 A3P250
      Package             208 PQFP
      Add Files           ex07\source\counter.vhd
      
    • Click the Synthesis button
    • When synthesis is complete Close Synplify or Precision
    • Click Place > Route Designer button
      Designer launches and prompts you to confirm some project settings
    • Accept the defaults
  3. Now you can set constraints
    • Click the Constraints Editor button
    • When the Compile Options dialogue appears, accept the defaults by clicking OK
  4. The SmartTime tool launches. You are now going to enter a constraint for the clock
    • Select menu Actions > Constraint > Clock
    • Select clock source to be Clock
    • Set the Period to 25 ns
    • Leave the Duty Cycle at 50%
    • Click OK
    • Select menu File > Commit
    • Close SmartTime
  5. Now you can view the timing results from Designer
    • Click the Layout button
    • Click Timing Analyzer

SmartTime reopens with the Summary report showing. Here you can see the maximum frequency for Clock after the layout and routing has been done. The external setup and hold times are shown along with the maximum and minimum Clock to out times.