Timing Constraints and Timing Analysis

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Setting Timing Constraints

Setting accurate timing constraints is an important part of the design flow. You will now set up some global constraints and analyze the results.

These instructions assume you are starting a new project. If you already have a project skip the first step.

  1. Set up a project as follows:
    • Start Vivado and click on Create Project
    • Next
    • Set project location to ... ex07\implemement\xilinx_zedboard, Project Name to "counter", Next
    • RTL Project, Next
    • Add Sources - add your design, ex07\source\counter.vhd, Next
    • Add Constraints (optional), Next (you will create a constraints file shortly)
    • Click on Boards, Select the Zedboard, Next
    • Finish
  2. Next, we need to open the constraint editor:
    • If you have not yet done so, click Run Synthesis in the Flow Navigator
    • Click Open Synthesized Design in the dialog box that appears at the end of synthesis or in the Flow Manager
    • Click Edit Timing Constraints (an option under Open Synthesized Design in the Flow Manager)
  3. The Timing Constraints Editor opens.
    • In the left pane of the Timing Constraints tab, make sure Create Clock(0) is highlighted.
    • Double-Click on the message "Double click to create a Create Clock Constraint" in the right pane
    • In the Source Object:, click ... The Specify Clock Source Objects dialog appears. Click Find
    • A list of ports appears. Double click Clock in the results. This will move it into the Selected Names: section.
    • Click Set to close the Specify Clock Source Objects dialog.
    • You can now edit the Waveform - but the default of 10ns is good enough, so click OK to save this constraint, close the Timing Constraint editor, saving any required files when prompted.
  4. Next you can implement the design and then look at the performance relative to the clock constraint you have specified
    • Click Run Implementation in the Flow Manager
    • You may be asked to save the project (because new constraints have been added) - click Save
    • You may then be warned that the synthesis may go out-of-date. If so, click OK
    • If you are prompted to Create a new [constraints] file, type a File name: counter and click OK
    • Finally (for now), answer Yes if asked to run Synthesis again
  5. When Place & Route has finished,
    • The Implementation Completed dialog may appear; if it does, select Open Implemented Design, OK
    • If prompted, close the 'Synthesized Design'
    • Click on the 'Timing' tab at the bottom of the Vivado IDE
    • The Design Timing Summary shows whether or not the timing constraints were met.
    • Click on the Worst Negative Slack (WNS) value
    • The critcal path will be selected in the Timing Summary report. If the timing constraints were met, this is the path that is nearest to failing; if the constraints were not met, it is the path that is failing by the largest amount.
      The placement of the cells in the critical path will be displayed in the Device view. Depending on how the tool is set up you will either see the routing or a 'ratsnest' showing the connectivity.
    • To see a schematic of the critical path, click the Schematic icon just above the paths, or press the F4 key

If a board is available, you can now go on to download your design using the do_zedboard.bat or do_zedboard.sh script provided, as in previous exercises.