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First, set up a new RTL project in Vivado in the ex02\simulate directory. You don't need a constraints (XDC) file. If you can remember the basics of creating a project click here; otherwise work through the following steps.
vivado &
Project Name ex02sim Location browse to the ex02\simulate directory
Board Zedboard Development and Evaluation board
xsim.elaborate.rangecheck
xsim.elaborate.debug_level
The project is now set up and you are ready to start fixing the errors in the VHDL files.
[VRFC 10-91] s1 is not declared [file.vhd:21]
You will now learn how to use some of the debugging facilities of the simulator.
run 15 ns
If you edit a source file while the simulator is running, then you need to re-compile the file. One way to do this is to quit the simulator, then launch it again. However there is a faster way.
When you have finished, close Vivado by selecting File > Exit.
If you added extra signals to the waveform window, but didn't save them in a waveform configuration file, you may now be prompted to save them and to add the resulting waveform configuration file to the project.
Done!