Creating a RAM using the IP Catalog

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Generating a RAM

For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM. You will generate the same RAM as above, but this time using Xilinx Vivado IP.

  1. Start Vivado
    • (Windows) Start Menu > Programs > Xilinx Design Tools > Vivado nnnn.m > Vivado nnnn.m or use the link on the desktop
      (Linux) type 'vivado &' in a shell
  2. You can run the IP generator within a project or standalone. We will run it standalone.
    • Click Manage IP > New IP Location
    • In the Create a New IP Location dialog, click Next
    • In the Manage IP Initial Settings dialog set
      Part                  ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1)
      Target Language       VHDL
      Target Simulator      (select what you are using)
      Simulator Language    VHDL
      Default IP location   ex09/source/ram1k8core
      
    • Click Finish
    • If prompted to create the directory, click OK
  3. Customise the IP:
    • In the IP Catalog, select Memories & Storage Elements > Rams & Roms & BRAM > Block Memory Generator
    • Right click and select Customize IP
    • Set the Component Name to ram1k8cgen
    • In the Basic tab set:
       Interface Type     : Native
       Memory Type        : Single Port RAM
       ECC Options        : No ECC
       Write Enable       : unchecked
       Algorithm Options  : Minimum area
       
    • Click the Port A Options tab. Set:
       Write Width                : 8
       Write Depth                : 1024
       Enable Port Type           : Always Enabled
       Primitives Output Register : unchecked
       
    • Click the Summary tab and check the settings. You should see
       Memory Type                        : Single Port Memory
       Block RAM resource(s) (18K BRAMS)  : 1
       Block RAM resource(s) (36K BRAMS)  : 0
       Total Port A Read Latency          : 1 Clock Cycle(s)
       Address Width A                    : 10
      
      If correct, click OK
    • In the Generate Output Products dialog, click Generate. (If a window appears warning about out-of-context module run, click OK.)
  4. In the pane at the top left, click the tab Sources. Have a look to see what has been generated. Shortly, you will need the implementation template ram1k8cgen.vho
  5. You will now create a RAM architecture that uses the generated block RAM.
    • Open the file ex09\source\ram1k8.vhd which has your original design.
    • Copy the first architecture then rename the copy to Xilinx. Delete all the existing code in the copy leaving only the architecture declaration, the word begin, and the end.
    • IMPORTANT! Comment out the first RTL architecture, so there is only one architecture in the file (the one called Xilinx)
    • In the new architecture, create a component declaration of the generated RAM. To do this you can copy the component declaration from the file ex09\source\ram1k8core\ram1k8cgen\ram1k8cgen.vho. You can access this from the Sources tab and paste it in front of the begin of your new architecture.
    • Using the example in the same file, create a component instantiation of the generated RAM and connect it to the entity ports like this:
      ram1k8cgen_inst : ram1k8cgen
      port map (
      clka => clock,
      dina => datain,
      addra => address,
      wea(0) => we,  -- note wea(0) !
      douta => dataout);
      

      Note that port wea is a 1 bit wide vector!
    • Finally, close the IP project using menu File > Close Project.

Synthesize the design with the Generated RAM

You are going to synthesize the design that uses the RAM again, but this time using the generated RAM instead of the one that was inferred from the RTL VHDL process.

The key is the .xci file that the Manage IP tool created. This is the file ex09\source\ram1k8core\ram1k8cgen\ram1k8cgen.xci

This file contains information which tell the Vivado synthesis tool how to find the underlying RAM model so that it can be synthesized. All we have to do is edit the download script!

  1. Return to the project that you originally used to synthesize the RTL version of the RAM. (This may be in the ex09\simulate directory.)
    • Open the project
    • In Sources - Hierarchy right-click on ram1k8 - Xilinx and choose Set as Top (if not already highlighted)
  2. Add the generated RAM IP to the project:
    • In the Flow Navigator under Project Manager click on Add Sources
    • Select Add existing IP and click Next
    • Click on the green cross and select Add Files...
    • Find ex09/source/ram1k8core/ram1k8cgen/ram1k8cgen.xci and click OK
    • In the Add Sources dialog click Finish
    • Run Synthesis
  3. When synthesis has completed,
    • Open the Synthesized Design
    • Display the schematic
    • In the schematic you should see ram1k8cgen_inst, under which are several layers of hierarchy with the block RAM at the lowermost level.

Next, you could download the design with the generated RAM (if a board is available) or simulate the generated RAM. To simulate, click here.


Downloading the generated RAM to the Zedboard Board

To use the provided script to download the generated RAM, you need to modify the script to include the .xci file.

  1. Edit the do_zedboard.tcl script
    • Open the file ex09\implement\xilinx_zedboard\do_zedboard.tcl in an editor
    • Add the first line below to the list of source files, in front of the ram1k8.vhd (there's a commented out line for you to copy if necessary)
                    
      ../../source/ram1k8core/ram1k8cgen/ram1k8cgen.xci
      ../../source/ram1k8.vhd
      
  2. Just in case, delete the existing xilinx project created from your first download by deleting the folder ex09\implement\xilinx_vivado\ex09proj. Alternatively, rename the project in the script: look for the line beginning
    set project_name
  3. To download the design
    • If necessary, open a command prompt by running ex09\implement\xilinx_zedboard\openhere.bat
    • Run do_zedboard.bat (Windows) or do_zedboard.sh (Linux), watching carefully for any errors that might occur. If something goes wrong, you can look at the reports by opening the file ex09proj\ex09proj.xpr in Vivado, and looking at the reports.

You have completed the download of the generated ram using Vivado IP!


(If you have time) Simulating the IP RAM

You don't need to compile any libraries if you are using the Vivado Simulator; the IP libraries are built in.

If necessary edit the testbench to instance the architecture Xilinx of Ram1k8

You have a choice of using the existing project, which may be the one that you used for synthesis, or modifying the simulation script.

Existing Project

  1. Make sure that the project is set up to use the architecture that contains the generated RAM:
    • In Sources - Hierarchy expand Simulations Sources and sim_1
    • Make sure that the VHDL architecture with the generated RAM appears under the testbench
  2. Run behavioral simulation from the Flow Navigator in the usual way
  3. In the Behavioral Simulation window,
    • Check that the correct version of the RAM was used by expanding the hierarchy
    • You should see several levels of hierarchy under the instance of the top-level RAM (ram1k8).

Done!

Using the Script

  1. To simulate using the provided script,
    • Change to the ex09\simulate directory
    • Edit do_VivadoXsim.tcl
    • Add ../source/ram1k8core/ram1k8cgen/ram1k8cgen.xci on a separate line above ../source/ram1k8.vhd:
      # design files
      set vhdl_files    {
                          ../source/ram1k8core/ram1k8cgen/ram1k8cgen.xci
                          ../source/ram1k8.vhd
      }        
      It doesn't matter that it is not a VHDL file!
    • Although you don't need to, you could also rename the project: look for the line beginning
      set project_name
  2. Run the script:
    • Use do_VivadoXsim.bat (Windows) or do_VivadoXsim.sh (Linux)
  3. In the Behavioral Simulation window, you can check that the correct version of the RAM was used by expanding hierarchy

Done!