Simulating a Gate-Level Netlist (from Libero) in ModelSim

  1. First test the RTL version using the given test bench.
    • Launch Modelsim and then set the working directory to:
    • ex06/simulate
      
    • Create a new working library.
    • Compile the counter and test bench files:
    •         ex06/source/counter.vhd
              ex06/source/counter_tb_pack.vhd
              ex06/source/counter_tb.vhd
              ex06/source/cfg_rtl.vhd
      
    • Simulate the configuration cfg_rtl. The tests pass if the OK signal remains true throughout.
  2. Now, to generate at gate-level netlist, follow the instructions in the README_Libero HTML file.
  3. To simulate the gate-level netlist, you will need to compile the generated simulation model in ModelSim. This references a library called proasic3. If you are using ModelSim Actel Edition, a precompiled version of that library is provided and so you can miss out this step. If you are using any other version of ModelSim, you will need to compile the proasic3 library yourself:
    • Then, select menu File > New > Library...
    • Create a new library and a logical mapping to it called proasic3 (use the same name for the Library Name and the Library Physical Name)
    • Select menu Compile>Compile... and in the Compile Source Files dialogue, select Library: proasic3 from the drop-down list.
    • Browse to the directory in which the Actel Libero software is installed, and from there to the subdirectory
    • Designer/lib/vtl/95
      
    • Compile this file:
      proasic3.vhd
      
  4. Compile the gate-level netlist into a new library:
    • Create a new library called
    • gate_lib
      
    • Compile the gate-level netlist into this library.
    • ex06/synthesize/ex06proj/designer/impl1/Counter_ba.vhd
      
  5. Compile the gate-level configuration into the library you created for RTL simulation (not gate_lib):
  6. ../source/cfg_gate.vhd
    
  7. Next select the gate-level configuration and
    • Select menu Simulate > Start Simulation...
    • Expand the library containing the configuration and select the gate-level configuration (without clicking on OK):
    • ../source/cfg_gate.vhd
      
    • Change the resolution to ps.
    • Click on the SDF tab
    • Click on the "Add..." button and browse to find the SDF file, then click on "Open".
    • ex06/synthesize/ex06proj/designer/impl1/Counter_ba.sdf
      
    • You must now select a region. Type /uut.
    • Set the delay to max using the drop-down list.
    • Click on OK to close the Add SDF dialog.
    • Click on OK to close the Start Simulation dialog.

Run the simulation in the usual way. Take a careful look to the waveform and messages in the transcript window. You should see the outputs are delayed by real delays.