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Simulation with Aldec Active-HDL (Windows)

After starting the tool...

  1. License configuration - Leave at "EE Mixed Design Entry", click Next
  2. Create a workspace
    • Select the option "Create new workspace"
    • Click OK
    • Type in a workspace name (e.g. "DoulosTraining")
    • Browse to c:\training
    • Make sure "Add New Design to Workspace" is checked
    • Click OK
  3. To set up the design...
    • In the New Design Wizard, select "Add Existing Resource Files"
    • Click next
    • Click "Add Files..."
    • Browse to the ex01\source directory and highlight logic.vhd and logic_tb.vhd (you can use Click / Shift Click to do that)
    • Once you've added both files, make sure "Make local copy" is not checked, and click Open
    • Click Next
    • Make sure the Default HDL Language: is VHDL, click Next
    • Type in a design name, e.g. ex01, and a library name, e.g. ex01lib
    • Click Next
    • Click Finish
  4. To compile all the files
    • Menu Design > Compile All with File Reorder
  5. Menu Simulation > Initialize Simulation
  6. Right click on LOGIC_TB(BENCH) at the left and select Add To Waveform
  7. Menu Simulation > Run
  8. If a dialog appears "Simulation has finished. There are no more vectors to simulate", click OK

Done!


Simulation with Modelsim SE/Questasim (Windows)

  1. Menu File > Change Directory... and browse to this folder
  2. Create a library
    • Menu File > New > Library...
    • Make sure the option "Create a new library and a logical mapping to it" is selected.
    • Leave the name Work as the library name
    • Type a suitable name for the Library Physical Name, e.g. ex01lib
    • Click OK
  3. To compile each file
    • Menu Compile > Compile...
    • Browse to the source directory
    • Click Default Options...
    • Uncheck box Use vopt flow
    • Click OK
    • Highlight logic.vhd
    • Click Compile (If asked to create a library, click Yes)
  4. Repeat the previous step for logic_tb.vhd (you don't have to set the Default Options again!)
  5. Menu Simulate > Start Simulation...
    • Click '+' to expand work
    • Highlight logic_tb
    • Make sure Enable Optimization is off
    • Click OK
  6. Right click on logic_tb at the left and select Add > To Wave > All Items in Region
  7. Menu Simulate > Run > Run -All

Done!


Xilinx ISim (ISE)

NOTE:If you are using Series 7 devices, you should be using Vivado/XSim - click here

  1. Start Xilinx ISE Project Navigator as follows
    • (Windows) Start the Xilinx ISE Project Navigator from the Windows Start menu or a desktop icon.
    • (Linux) Type this command in a terminal window:
      ise &
  2. Create a new project:
    • Select menu File > New Project...
    • Set the following details
      Name                    ex01sim	
      Location                browse to the ex01/simulate directory	
      Top Level Source Type   HDL
      
    • Click Next
    • Set the Project Settings:
    • Product Category      General Purpose	(or leave at All)	
      Family                Spartan3E	
      Device                XC3S500E	
      Package               FG320	
      Speed                 -4	
      Synthesis Tool        XST (VHDL/Verilog)	
      Simulator             ISim (VHDL/Verilog) 	
      Preferred Language    VHDL
      
    • Click Next
    • Click Finish
  3. Select menu Project>Add Source...
  4. Browse to ex01/source, highlight logic.vhd and logic_tb.vhd, and click Open
  5. When the Adding Source Files... dialog box appears, click OK
  6. In the main ISE Project Navigator window Ensure that the "View" button has Simulation selected, and the drop down list at the top left is set to "Behavioral". Also make sure LOGIC_TB – BENCH is highlighted in the Hierarchy pane.
  7. Run the Simulation
    • If necessary, expand the + next to "ISim Simulator in the Processes: pane", right-click on "Simulate Behavioral Model" and select "Process Properties".
    • In the Simulation Run Time setting, replace "1000 ns" with "all", then click OK
    • Double-click "Simulate Behavioral Model"

The ISim window should appear in a few moments, with the "Instances and Processes" pane to the left, the "Objects" pane in the centre and the waveform viewer on the right. Because the Simulation Run Time was set to "all", the simulation should have run. You can study the waveforms by using the buttons to the left of the waveform pane: zoom in and out, move the cursor(s) and use the ruler to check time differences. If you accidentally close a pane, use View > Panels to show it again, or select Layout > Restore Default Layout.

When you have finished, close ISim by selecting File > Exit.

Done!


Xilinx XSim (Vivado)

NOTE:If you are using older devices (not Series 7 - for instance Spartan 3 or Spartan 6), you should be using ISE/ISim - click here

  1. Start Xilinx Vivado as follows
    • (Windows) Start the Vivado tool from the Windows Start menu or a desktop icon.
    • (Linux) Type this command in a terminal window:
      vivado &
  2. Create a new project:
    • Select menu File > New Project...
    • The Create a New Vivado Project dialog appears: Click Next
    • Set the following details
      Project Name            ex01	
      Location                browse to the ex01\simulate directory	
      
    • Leave Create project subdirectory checked
    • Click Next
  3. In the Project Type dialog:
    • Select RTL Project
    • Click Next
  4. In the Add Sources dialog:
    • Select the Target/Simulation languages: to VHDL
    • Click the green cross then "Add Files..."
    • In the Add Source Files dialog, browse to ex01\source
    • Highlight both logic.vhd and logic_tb.vhd, and Click OK
    • Make sure Copy Sources into project is NOT checked
    • Vivado will attempt to identify which sources are only for Simulation, and which are for both Simulation & Synthesis. Check the settings it has chosen in the column HDL Source For – and make sure the testbench, logic_tb.vhd, is set to 'Simulation Only'.
    • Click Next
  5. In the Add Constraints (optional) dialog, you can add a constraint file. For this simulation tour we will not add any constraints.
    • Click Next
  6. Select the default part - click the green Board icon
    Board        Zedboard Development and Evaluation board
    
  7. The New Project Summary appears
    • Assuming everything is OK, Click Finish
  8. Make sure you are ready for simulation
    • In the Vivado IDE, there is a pane at the left labeled Flow Navigator. Click on Settings and then in the dialog that opens, click on Simulator (under Project Settings on the left hand side)
    • In the Project Settings for Simulation, set the Target Simulator: to Vivado Simulator
    • The Simulation top module name: should be set to logic_tb
    • In the Elaboration tab at the bottom of the window, make sure
      xsim.elaborate.rangecheck
      is checked.
    • Set the
      xsim.elaborate.debug_level
      option as all
  9. You can now set other simulation settings
    • Click on the Simulation tab. In this tab you may set the Simulation Run Time. It defaults to 1000ns. Set it to the word all (meaning "run until there is nothing more to do"). Click OK.
  10. To run simulation
    • In the Flow Navigator, click Run Simulation.
    • In the dialog that appears, select Run Behavioral Simulation
    • In the wave window you should see a waveform for each of the signals at the top level of your simulation. To see the full waveforms, right click over the waveforms and select menu Full View, or click the Zoom Fit button to the left of the waveforms.
    • Inspect the waveforms and check that they are as expected.
  11. When you have finished,
    • Close the simulator by clicking the cross at the top right of the 'Behavioral Simulation' window.
    • Click OK to Confirm Close.
  12. Quit Vivado

Now follow the instructions in the README.html file in ex01/implement/xilinx_zedboard