Synthesis and Place and Route

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Xilinx ISE Synthesis and Place & Route

This section describes synthesis use Xilinx's XST synthesis tool, followed by Place & Route in ISE. If you are using a third party synthesis tool (such as Synopsys Synplify, Mentor Precision), follow those instructions instead.

  1. Run ISE - windows menu
    ISE Design Suite NN.M > ISE Design Tools > Project Navigator
    Linux
    ise &
  2. Create a project:
    • File > New Project
    • Name: ex01proj
    • Location: <this folder> i.e. ex01\implement\xilinx_spartan3E
    • (!IMPORTANT!) Top-level source type: HDL
    • click Next
  3. Set the Project Settings
    Product Category    General Purpose	(or leave at All)	
    Family              Spartan3E	
    Device              XC3S500E	
    Package             FG320	
    Speed               -4	
     	
    Synthesis Tool      XST (VHDL/Verilog)	
    Simulator           ModelSimSE VHDL (or ISIM if you used ISIM)	
    Preferred Language  VHDL
    
  4. Click Next
  5. Click Finish
  6. Add the sources:
    • Select menu Project>Add Source...
    • Browse to ex01/source, highlight logic.vhd and click Open.
    • When the Adding Source Files... dialogue box appears, click OK
  7. The main project window will appear - make sure the View: at the top left is set to Implemementation:
  8. To synthesize the design using XST:
    • Make sure LOGIC – RTL is highlighted in the Hierarchy pane at the left.
    • Double click on the Synthesize – XST process in the Processes pane at the left
    After a while, a green tick will appear: you can view the synthesized design, either as RTL, or mapped onto technology primitives.
  9. To view the RTL Design
    • Click the + next to Synthesize – XST in the Processes pane. This will show more options.
    • Double click View RTL Schematic
      A dialogue box will appear, asking you to set RTL/Tech Viewer Startup mode.
    • Select Start with a schematic of the top-level block, and click OK
  10. To view the same circuit mapped to the technology library:
    • In the Processes pane, double click View Technology Schematic
      A dialogue box will appear, asking you to set RTL/Tech Viewer Startup mode.
    • Select Start with a achematic of the top-level block, and click OK

The next step is Place &Route. At the moment, the tool does not know which pins should be used on the target hardware. The pin locations are supplied in a user constraints file (UCF).

  1. To attach the constraint file to the project
    • In the Hierarchy: pane at the top left, highlight the project ex01proj by clicking on it once, right click over the project name (ex01proj) and select Add Source...
    • Browse to ex01/implement/xilinx_spartan3E/spartan3E.ucf
    • Click Open
    • Click OK
  2. You will see that the UCF file has been added – you can see it by clicking the little + next to the project top-level: LOGIC - RTL in the Hierarchy: pane. To view the UCF file:
    • Highlight spartan3E.ucf in the Hierarchy: pane
    • In the Processes: pane, click the + next to User Constraints
    • Double click Edit Constraints (Text)
      The file will open. It contains the constraints to set the pin locations and the I/O standard for the top-level VHDL ports.
    • Close the file
  3. The next step is to place and route the design.
    • Make sure the top-level (LOGIC – RTL) is highlighted in the Hierarchy: pane
    • In the Processes: pane, double click "Implement Design"

After a while, a green tick should appear. If it doesn't consult your course leader.

Click here for instructions to download the design.


Synthesis with Synopsys Synplify Pro

  1. Run synplify pro. On Windows use the start menu,
    on Linux type
    synplify_pro&
    If a "tip" appears, click OK
  2. Create a project
    • File > New...
    • select Project File (Project)
    • Browse to this folder
    • Set the name to (for example) ex01
    • click OK
  3. Click Implementation Options... button and set
    Xilinx Spartan 3E
    XC3S500E
    FG320
    -4
    
    Click OK
  4. Click the button Add File...
    • Browse to logic.vhd
    • Click <-Add
    • Click OK
  5. Click Run
  6. to view the graphics, use menu HDL Analyst > RTL > Hierarchical View
    or for the Technology view HDL Analyst > Technology Hierarchal View
  7. The synthesized netlist is in rev_1\logic.edf

Done!

You can quit the tool.

To Place and Route and download the design, go to Place and Route


Implementation with Xilinx ISE (EDIF input from 3rd party synthesis tool)

  1. Run ISE - windows menu
    ISE Design Suite NN.M > ISE Design Tools > Project Navigator
    Linux
    ise &
  2. Create a project:
    • File > New Project
    • Name: ex01proj
    • Location: <this folder>
    • (!IMPORTANT!) Top-level source type: EDIF
    • click Next
  3. Set up the inputs:
    • Input design: browse to logic.edf you created from synthesis
    • Constraint file: browse to spartan3E.ucf
    • Uncheck the two check-boxes for copying (that is don't copy into project)
    • Next
  4. Set
    Product Category    General Purpose	(or leave at All)	
    Family              Spartan3E	
    Device              XC3S500E	
    Package             FG320	
    Speed               -4	
    
  5. Next
  6. Finish
  7. To do place and route Double-click Generate Programming File
    After a while, a green tick should appear. If it doesn't consult your course leader.

Click here for instructions to download the design.


Downloading to the Spartan 3E Board

  1. Make sure the board and JTAG USB cable are plugged in and switched on.
  2. Double-click Configure Target Device (click OK if prompted)
  3. Double-click Boundary Scan
  4. Right-Click on the right (over the blue message) and select Initialize Chain
  5. Cancel any dialogue boxes that appear then...
    • Highlight the xc3s500e
    • Right-click and select Assign New Configuration File
  6. Browse to logic.bit (in the Xilinx project ex01proj)
  7. Click Open
  8. If prompted to "Attach SPI or BPI Rom" click No
  9. Right-click on the FPGA again, and select Program - If a dialogue appears, click OK

Now test if your downloaded design is working!


Testing the board

The 4 inputs are on slide/DIP switches SW0, SW1, SW2, SW3 at the lower right of the board. The 4 outputs are on the LEDs LD0, LD1, LD2, LD3. The pin numbers are printed on the board, so you can relate them back to the VHDL ports by looking in the spartan3E.ucf file.