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For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM. You will generate the same RAM as above, but this time using Xilinx Vivado IP.
Part ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1) Target Language VHDL Target Simulator (select what you are using) Simulator Language VHDL Default IP location ex09/source/ram1k8core
Interface Type : Native Memory Type : Single Port RAM ECC Options : No ECC Write Enable : unchecked Algorithm Options : Minimum area
Write Width : 8 Write Depth : 1024 Enable Port Type : Always Enabled Primitives Output Register : unchecked
Memory Type : Single Port Memory Block RAM resource(s) (18K BRAMS) : 1 Block RAM resource(s) (36K BRAMS) : 0 Total Port A Read Latency : 1 Clock Cycle(s) Address Width A : 10
ram1k8cgen_inst : ram1k8cgen port map ( clka => clock, dina => datain, addra => address, wea(0) => we, -- note wea(0) ! douta => dataout);
You are going to synthesize the design that uses the RAM again, but this time using the generated RAM instead of the one that was inferred from the RTL VHDL process.
The key is the .xci file that the Manage IP tool created. This is the file ex09\source\ram1k8core\ram1k8cgen\ram1k8cgen.xci
This file contains information which tell the Vivado synthesis tool how to find the underlying RAM model so that it can be synthesized. All we have to do is edit the download script!
Next, you could download the design with the generated RAM (if a board is available) or simulate the generated RAM. To simulate, click here.
To use the provided script to download the generated RAM, you need to modify the script to include the .xci file.
../../source/ram1k8core/ram1k8cgen/ram1k8cgen.xci ../../source/ram1k8.vhd
set project_name
You have completed the download of the generated ram using Vivado IP!
You don't need to compile any libraries if you are using the Vivado Simulator; the IP libraries are built in.
If necessary edit the testbench to instance the architecture Xilinx of Ram1k8
You have a choice of using the existing project, which may be the one that you used for synthesis, or modifying the simulation script.
Done!
# design files set vhdl_files { ../source/ram1k8core/ram1k8cgen/ram1k8cgen.xci ../source/ram1k8.vhd }