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For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM. You will generate the same RAM as above, but this time using the Xilinx CORE Generator tool.
ram1k8cgen_inst : ram1k8cgen port map ( clka => clock, dina => datain, addra => address, wea(0) => we, -- note wea(0) ! douta => dataout);
Click here for instructions to modify the script and download the design.
The VHDL is now complete - but how do the implementation tools know what to do? The implementation information is held in the file ex09\source\ram1k8core\ram1k8cgen.ngc – in a proprietary Xilinx format. This file could be placed in the Xilinx project directory. Alternatively the do_spartan3e.tcl script could be told where to find the ngc file.
set source_directory ../../../source/ram1k8core
spartan3e_top.syr Synthesis Report spartan3e_top.bld Translate report spartan3e_top_map.mrp Map report spartan3e_top.par Place & Route report
Alternatively, you can view the reports in ISE by loading the project file, ex09\implement\xilinx_spartan3e\spartan3e\spartan3e_top.ise.
You have completed the download of the generated ram using CoreGen!
To simulate a design that contains a CORE Generator instance, you will need to compile the generated model in your simulator. In this exercise, that is the file
ex09\source\ram1k8core\ram1k8cgen.vhd
You should also edit the testbench in ram_tb.vhd to select the second architecture of the RAM and compile that.
The generated RAM model references a library called XilinxCoreLib. If you are using ModelSim XE, Aldec Active-HDL, or Xilinx ISIM, a precompiled version of that library is provided and so you can proceed immediately to simulate the design.
If you are using Modelsim on a Doulos PC, then the library is again already compiled, and you can simulate straight away - click here
Only follow the instructions here if none of the above applies!. If in doubt, ask your course leader!
source\ram1k8core\ram1k8cgen.vhd