Advanced VHDL ex06 - ISE Simulation and Implementation

These instructions assume you are starting a new project.

  1. Run ISE - windows menu
    ISE Design Suite NN.M > ISE Design Tools > Project Navigator
    Linux
    ise &
  2. Create a project:
    • File > New Project
    • Name: ex06proj
    • Location: <this folder> i.e. ex06\synthesize
    • Top-level source type: HDL
    • click Next
  3. Set the Project Settings
    Product Category    General Purpose	(or leave at All)	
    Family              Spartan3E	
    Device              XC3S500E	
    Package             FG320	
    Speed               -4	
     	
    Synthesis Tool      XST (VHDL/Verilog)	
    Simulator           choose	
    Preferred Language  VHDL
    
  4. Click Next
  5. Click Finish
  6. Add the sources:
    • Select menu Project>Add Source...
    • Browse to ex06/source, highlight Counter.vhd Counter_tb.vhd Counter_tb_pack.vhd and cfg_rtl.vhd.
    • Click Open.
    • When the Adding Source Files... dialogue box appears, make sure the Association for Counter_tb.vhd Counter_tb_pack.vhd and cfg_rtl.vhd is Simulation and for Counter.vhd is All.
    • Click OK
  7. If you wish to simulate using Isim (ie within ISE), at this point you need to simulate the RTL (otherwise miss out this step):
    • The main project window will appear - make sure the View: at the top left is set to Simuation.
    • Right click in the Hierarchy pane and select Manual Compile Order. Enter cfg_rtl in the Top Module field.
    • Right click on cfg_rtl.vhd in the Hierarchy pane. In the Processes pane, double click on Simulate Behavioural Model. Check that the simulation passes - the OK signal should remain true throughout.
    • Close the simulation.
  8. Now, in the main project window set the View at the top left to Implementation and set the top module to counter.
  9. Apply timing constraints as follows. These will be written to a user constraints file (UCF).
    • In the Processes: pane, click the + next to User Constraints
    • Double-click Create Timing Constraints
  10. Synthesis and Translate will run and then you will be asked if you would like a UCF file created.
    • Click “Yes” and the Xilinx Constraints Editor should open.
    • In the Constraint Type pane, make sure you can see Clock Domains, Inputs, and Outputs under the heading Timing Constraints. If you can’t, click the + next to Timing Constraints. In the pane Unconstrained Clocks, double-click the word Clock.
    • In the Clock Period form, set the Time: to 10 and click OK. This gives a clock period of 100 MHz.
    • Highlight Inputs in the Constraint Type pane. Right-click in the row under the words "Pad Group" at the top left, and select Create Constraint.
    • The Create Setup Time(OFFSET IN) dialogue appears. Click Next.
    • The default values should be correct (10 in the two cells at the left). Click Finish.
    • Highlight Outputs in the Constraint Type pane. Right-click in the row under the words "Pad Group" at the top left, and select Create Constraint.
    • The Create Clock to Pad (OFFSET OUT) dialogue appears. The default value of 10 in the External Clock to Pad (offset out): cell is all right, so click OK.
    • Save the UCF file and close the Constraints Editor (don’t close the ISE Project Navigator).
  11. A VHDL gate-level netlist will not be created by default. To create one...
    • ...click on Implement Design in the Processes: pane with the right mouse button and select Process Properties… (Note: if you cannot see the Processes: pane, click the Design tab at the left just above the Console pane).
    • Select the Category Place & Route Properties on the left and make sure the Property Generate Post-Place & Route Simulation Model is ticked.
    • Select the Category Simulation Model Properties on the left.
    • Set the value of the Simulation Model Target property to VHDL.
    • Click OK.
  12. You are now ready to place and route the design. When place & route has completed, the green tick appears in the Process pane.
    • Make sure the VHDL file is highlighted in the Hierarchy pane.
    • In the Processes: pane, double click Implement Design
  13. Find the worst-case clock frequency and pin timing:
    • In the Design Summary, under Design Overview, click Timing Constraints.
    • Write down Worst-case PERIOD and OFFSET = OUT – use figures in the “Best Case Achievable” column.
  14. The ISE Project Navigator should have created an SDF file and a VHDL gate level netlist. These will be in a sub-directory of the project (ex06/implement/ex06proj) called netgen/par. ISE uses the following names for the netlist and SDF files:
    Counter_timesim.vhd	– Output VHDL gate level netlist	
    Counter_timesim.sdf	– SDF file
    
  15. If you did not specify Isim as your simulator, you can now quit ISE and follow the relevant README HTML file in the simuate directory. Otherwise, if you did select Isim (ie you wish to use ISE for simulation), then continue following these instructions.
  16. It is best to let the tool set up gate level simulation for you:
    • Set the View back to Simuation.
    • Remove cfg_rtl from the compilation (by removing the tick next to cfg_rtl.vhd)
    • Set the project back to automatic compile order – right click on the device name and make sure Manual Compile Order is not ticked.
  17. Now change the type of simulation:
    • in the drop down list above the Hierarchy pane, choose "Post-route" for simulation.
  18. Set up the simulation as follows:
    • Check that the testbench is highlighted in the Hierarchy pane
    • Right click Simulate Post-Place & Route Model in the Processes pane and select Process Properties...
    • Set the Property Display Level to Standard.
    • Set the Simulation Run Time to "all"
    • Specify Top Level Instance Name should be set to work.Counter_tb
    • ISim UUT Instance Name should be set to uut
    • Click OK
  19. To run the simulation:
    • Double-click Simulate Post Place & Route Model.

Take a careful look to the waveform and messages in the transcript window. You should see the outputs are delayed by real delays.