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For simple RAM models, it is possible to write code that directly generates a RAM. For more complex RAMs, and to access all the detailed features, you can use an IP generator to generate the RAM. For simplicity, we will generate the same RAM as befoer, but this time using the Microsemi/Actel SmartGen tool.
component block_ram is port(WD : in std_logic_vector(7 downto 0); RD : out std_logic_vector(7 downto 0); WEN : in std_logic; REN : in std_logic; WADDR : in std_logic_vector(9 downto 0); RADDR : in std_logic_vector(9 downto 0); RWCLK : in std_logic ); end component block_ram; signal we_b : std_logic;
we_b <= not we; UUT: block_ram port map ( WD => datain, RD => dataout, WEN => we_b, -- active low REN => we, -- active low WADDR => address, RADDR => address, RWCLK => clock );
Click here for instructions to download the design.
The VHDL is now complete. However the Libero Place & Route tool will not be able to find the RAM model unless the block_ram.vhd file is also compiled.
../../../source/block_ram.vhd ../../../source/ram1k8.vhd
You have completed the download of the generated ram using SmartGen!
To simulate a design that contains a SmartGen module, you will need to compile the generated simulation model in ModelSim. In this exercise, that is the file ex09/source/block_ram.vhd.
You will also need to modify the testbench (ex09/source/ram_tb.vhd) so that it instances the SmartGen module instead of the original model, which produces the embedded RAM.
The SmartGen module references a library called proasic3. If you are using ModelSim Actel Edition, a precompiled version of that library is provided and so you can proceed immediately to simulate the design.
proasic3.vhd
If you use the script, check the setting of the variable libero_path. The script must be executed from within ModelSim, either by using the 'do' command at the command prompt; or from the menu Tools > Tcl > Execute Macro...
You have now compiled the proasic3 library and are ready to simulate the design. However, you should set the simulation resolution to 1 ps in the Start Simulation dialogue. (Some versions of ModelSim have a default resolution of 1 ns.)
The compile script, do_modelsim.tcl, could be changed like this:
set top_level {-t ps mylib.ram_tb}
Change the compile script to include the file block_ram.vhd
Take a careful look to the waveform and messages in the transcript window.