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After starting the tool...
Done!
NOTE:If you are using Series 7 devices, you should be using Vivado/XSim - click here
ise &
Name ex01sim Location browse to the ex01/simulate directory Top Level Source Type HDL
Product Category General Purpose (or leave at All) Family Spartan3E Device XC3S500E Package FG320 Speed -4 Synthesis Tool XST (VHDL/Verilog) Simulator ISim (VHDL/Verilog) Preferred Language VHDL
The ISim window should appear in a few moments, with the "Instances and Processes" pane to the left, the "Objects" pane in the centre and the waveform viewer on the right. Because the Simulation Run Time was set to "all", the simulation should have run. You can study the waveforms by using the buttons to the left of the waveform pane: zoom in and out, move the cursor(s) and use the ruler to check time differences. If you accidentally close a pane, use View > Panels to show it again, or select Layout > Restore Default Layout.
When you have finished, close ISim by selecting File > Exit.
NOTE:If you are using older devices (not Series 7 - for instance Spartan 3 or Spartan 6), you should be using ISE/ISim - click here
vivado &
Project Name ex01 Location browse to the ex01\simulate directory
Board Zedboard Development and Evaluation board
xsim.elaborate.rangecheck
xsim.elaborate.debug_level
Now follow the instructions in the README.html file in ex01/implement/xilinx_zedboard