- First test the RTL version using the given test bench.
- Launch Modelsim and then set the working directory to:
ex06/simulate
- Create a new working library.
- Compile the counter and test bench files:
ex06/source/counter.vhd
ex06/source/counter_tb_pack.vhd
ex06/source/counter_tb.vhd
ex06/source/cfg_rtl.vhd
- Simulate the configuration cfg_rtl. The tests pass if the OK signal remains true throughout.
- Now, to generate at gate-level netlist, follow the instructions in the README_ISE HTML file.
- The gate-level netlist references the Xilinx SIMPRIM library. This library contains the design entities corresponding to the components in the netlist. If you are using ModelSim XE,
precompiled version of the library is provided and so you can miss out this step.
If you are using any other version of ModelSim, you will need to compile the library yourself:
- Select menu File > New > Library...
- Select the option Map to an Existing Library
- In the Library Name: type simprim
- In the Library Maps To: browse to C:\EDK_Libs\ModelSimSE<version>\simprim
- Compile the gate-level netlist into a new library:
- Create a new library called
gate_lib
- Compile the gate-level netlist into this library.
ex06/synthesize/ex06proj/netgen/par/Counter_timesim.vhd
- Compile the gate-level configuration into the library you created for RTL simulation (not gate_lib):
../source/cfg_gate.vhd
- Next select the gate-level configuration and
- Select menu Simulate > Start Simulation...
- Expand the library containing the configuration and select the gate-level configuration (without clicking on OK):
../source/cfg_gate.vhd
- Change the resolution to ps.
- Click on the SDF tab
- Click on the "Add..." button and browse to find the SDF file, then click on "Open".
ex06/synthesize/ex06proj/netgen/par/Counter_timesim.sdf
- You must now select a region. Type /uut.
- Set the delay to max using the drop-down list.
- Click on OK to close the Add SDF dialog.
- Click on OK to close the Start Simulation dialog.
Run the simulation in the usual way. Take a careful look to the waveform and messages in the transcript window. You should see the outputs are delayed by real delays.