These instructions assume you are starting a new project.
ise &
Product Category General Purpose (or leave at All) Family Spartan3E Device XC3S500E Package FG320 Speed -4 Synthesis Tool XST (VHDL/Verilog) Simulator choose Preferred Language VHDL
Counter_timesim.vhd – Output VHDL gate level netlist Counter_timesim.sdf – SDF file
Take a careful look to the waveform and messages in the transcript window. You should see the outputs are delayed by real delays.