Creating a RAM using Microsemi/Actel SmartGen

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Generating a RAM

For simple RAM models, it is possible to write code that directly generates a RAM. For more complex RAMs, and to access all the detailed features, you can use an IP generator to generate the RAM. For simplicity, we will generate the same RAM as befoer, but this time using the Microsemi/Actel SmartGen tool.

  1. Start the Libero tool.
    • Set the location to .\ex09\implement\microsemi_A3PE_Eval_Board and call it ex09gen. This will create a folder ex09gen in the folder .\ex09\implement\microsemi_A3PE_Eval_Board. Family is ProASIC3 with VHDL output. If there is no Catalog pane present, Select View > Windows > Catalog.
  2. In the Catalog pane
    • Expand Memory & Controllers
    • Double click on "Two Port RAM" in the Core Varieties pane.
  3. A dialogue box labelled "RAM: Create core" appears
    • Set Write Address Depth to 1024
    • Set Write Data width to 8
    • Set Read Address Depth to 1024
    • Set Read Data width to 8
    • Check Single clock
    • Uncheck reset
    • Uncheck Pipeline
    • Do not initialise RAM for simulation
    • Click Generate...
    • Call the new core block_ram and click ok
    • Close the window
  4. Files will be generated - block_ram.vhd is the simulation model. This is in the ex09gen\smartgen\block_gen folder.
    • Copy block_ram.vhd to the source folder
  5. You will now create a second RAM architecture that uses the generated block RAM.
    • Open the file source\ram1k8.vhd which has your original design.
    • Copy the first architecture then rename the copy. Delete all the existing code in the copy leaving only the architecture declaration, the word begin, and the end.
    • In the new architecture, create a component declaration of the block_ram. There isn't a template provided, so copy the entity declaration from block_ram.vhd and paste it in front of the word begin in your new architecture
    • Edit the declaration and change the word "entity" to "component" at the beginning and end. It should look like this:
        component block_ram is
          port(WD : in std_logic_vector(7 downto 0);
            RD : out std_logic_vector(7 downto 0);
            WEN : in std_logic;
            REN : in std_logic;
            WADDR : in std_logic_vector(9 downto 0);
            RADDR : in std_logic_vector(9 downto 0);
            RWCLK : in std_logic
          );
        end component block_ram;
      
        signal we_b : std_logic;
      
    • Create a component instantiation of the generated RAM, connect it to the entity ports like this:
        we_b <= not we; 
        UUT: block_ram
          port map (
            WD => datain,
            RD => dataout,
            WEN => we_b, -- active low
            REN => we, -- active low
            WADDR => address,
            RADDR => address,
            RWCLK => clock
          );
      

Click here for instructions to download the design.


Downloading the generated RAM to the Microsemi/Actel A3PE Eval Board

The VHDL is now complete. However the Libero Place & Route tool will not be able to find the RAM model unless the block_ram.vhd file is also compiled.

  1. Just in case, delete any existing project created from your first download by deleting the folder ex09\implement\microsemi_A3PE_Eval_Board\actel
  2. Edit the file ex09\implement\microsemi_A3PE_Eval_Board\do_actel.tcl and add the extra source file before ram1k8.vhd, as shown here:
    ../../../source/block_ram.vhd
    ../../../source/ram1k8.vhd
    
  3. To download the design
    • If necessary, open a command prompt by running ex09\implement\microsemi_A3PE_Eval_Board\openhere.bat
    • Run do_actel.bat, watching carefully for any errors that might occur.

You have completed the download of the generated ram using SmartGen!


(If you have time) Simulating the IP RAM

To simulate a design that contains a SmartGen module, you will need to compile the generated simulation model in ModelSim. In this exercise, that is the file ex09/source/block_ram.vhd.

You will also need to modify the testbench (ex09/source/ram_tb.vhd) so that it instances the SmartGen module instead of the original model, which produces the embedded RAM.

The SmartGen module references a library called proasic3. If you are using ModelSim Actel Edition, a precompiled version of that library is provided and so you can proceed immediately to simulate the design.

  1. If you are using any other version of ModelSim, you will need to compile the proasic3 library yourself. You can use the provided script simulate/compile_actel_proasic3.tcl or manually like this:
    • In ModelSim, select menu File > New > Library...
    • Create a new library and a logical mapping to it called proasic3 – use the same name for the Library Name and the Library Physical Name.
    • Select menu Compile>Compile... and in the Compile Source Files dialogue, select Library: proasic3 from the drop-down list.
    • Browse to the directory in which the Actel Libero software is installed, and from there to the subdirectory Designer\lib\vtl\95.
    • Compile this file:
      proasic3.vhd
      

If you use the script, check the setting of the variable libero_path. The script must be executed from within ModelSim, either by using the 'do' command at the command prompt; or from the menu Tools > Tcl > Execute Macro...

You have now compiled the proasic3 library and are ready to simulate the design. However, you should set the simulation resolution to 1 ps in the Start Simulation dialogue. (Some versions of ModelSim have a default resolution of 1 ns.)

The compile script, do_modelsim.tcl, could be changed like this:

set top_level  {-t ps mylib.ram_tb}

Change the compile script to include the file block_ram.vhd

Take a careful look to the waveform and messages in the transcript window.