Running a Gate-level Simulation in Active-HDL

  1. First test the RTL version using the given test bench.
    • Launch Active-HDL with either an existing or new workspace and then set up a new design:
    • Select Add Existing Resource Files then click Next.
    • Add Files...
    •         ex06/source/counter.vhd
              ex06/source/counter_tb_pack.vhd
              ex06/source/counter_tb.vhd
              ex06/source/cfg_rtl.vhd
      
    • Click Next.
    • On the Property Page, select the Vendor and Technology. Click Next.
    • On the New Design Wizard, enter the design name (ex06), the location (ex06/simulate), the name of the default working library. Click Next.
    • Click Finish.
  2. Simulate the configuration cfg_rtl. The tests pass if the OK signal remains true throughout.
  3. Now, to generate at gate-level netlist, follow the instructions in the appropriate README HTML file.
  4. To simulate the gate-level netlist, first create a new library into which the VHDL netlist will be compiled:
    • Select menu Design > Create Library...
    • Type the name of the library:
      gate_lib
    • Make sure Create Empty Library is not ticked, and click Next
    • Click Add Files... and add the gate-level netlist (don't add the SDF file).
    • Type the name of the library:
      gate_lib
    • Click Finish.
  5. The gate-level configuration of the testbench is in:
    ../../ex06/source/cfg_gate.vhd
    • Add and compile this file into the library you created for RTL simulation (not gate_lib).
    • In Design Browser, click the Files tab, then right click on cfg_gate and select Set as Top-Level
  6. To include the SDF file in the design
    • Select Add New File in the Design Browser and use the Add New File dialog to add an existing SDF file to the design.
    • Select menu Design > Settings...
    • In the Design Settings dialog, under Category: expand Simulation and click on SDF.
  7. In the line below the SDF file name, you will see the path of the design unit in the design hierarchy to which the SDF file applies.
    • Click in the Region field and type /Counter_TB/uut. (uut is the instance name of the counter component.)
  8. The Value field indicates whether to use the Minimal, Average or Maximal SDF delay values.
    • Click in the Value field and select Maximal from the drop-down list.
  9. The Load field allows you to enable and disable loading the SDF file, so that you can simulate either with delays or without them.
    • Click in the Load field and select Yes from the drop-down list, then Select OK.

Run the simulation in the usual way. Refer to the workbook for the remaining exercise instructions.