Advanced VHDL ex06 - Microsemi/Actel Libero Synthesis and Place & Route

This file describes and Place & Route using Microsemi/Actel Libero which uses Synopsys Synplify or Mentor Precision as its synthesis tool, followed by Place & Route in Microsemi/Actel Designer.

First make sure you have carried out the instructions in the Advanced VHDL workbook, exercise 6 in the section "RTL Simulation".

  1. Start Libero from the Windows Start menu, or a desktop icon.
  2. Create a new project as follows:
    • Select menu Project > New Project...
    • Set the following details:
      Project Name        ex06proj
      Location            browse to ex06\synthesize	
      Design Entry Type   VHDL
      
    • Click Next
    • Select Device, select the following details:
      Family:       ProASIC3
      Device:       A3P250
      Package:      208 PQFP
      Speed:        -2
      Core Voltage: 1.5
      Range:        COM
      
    • Click Next
    • Default I/O Technology:   LVTTL
      
    • Click Next
    • Add HDL Source Files: Click "Link File". Add the file ..\source\counter.vhd: Click Next
    • Add Constraints: Click Finish
  3. You are now ready to synthesize and optimize your design.
    • Select Project->Tool Profiles->Synthesis and click the radio button next to either "Synplify Pro" or "Precision RTL Synthesis".
    • Right click "Synthesize" in the "Design Flow" pane and select "Run". Synthesis will run.
    • Right click "Compile" in the "Design Flow" pane and select "Run". Optimization will run.
  4. You are now ready to Place and Route your design.
    • Right click "Place & Route" in the "Design Flow" pane and select "Open interactively". The Designer application window appears.
    • In Designer click the Layout button.
    • Accept the default layout options, click OK
  5. Now you are ready to generate back-annotation files.
    • Click the Back-Annotate button
    • Make sure there is a dot (".") in the "Extracted files directory" window.
    • Accept the default values and click OK

For instructions to simulate the gate-level netlist, please refer to the relevant README file in the simulate directory.