Running exercise 2

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Running exercise 2 in ISE
Running exercise 2 in Vivado
Running exercise 2 in ModelSim

ISE

These instructions assume you are starting a new project.

Set up:

Create a new project:

Select menu File > New Project...

Set the following details

Name                    ex02proj	
Location                browse to the ex02 directory	
Top Level Source Type   HDL

Click Next
Set the Project Settings:

Product Category      General Purpose	(or leave at All)	
Family                Spartan3E	
Device                XC3S500E	
Package               FG320	
Speed                 -4	
Synthesis Tool        XST (VHDL/Verilog)	
Simulator             ISim (VHDL/Verilog) 	
Preferred Language    VHDL

Click Next
Click Finish

Select menu Project>Add Source... Browse to ex02, select exor2.vhd, exor2tb.vhd and click Open. When the Adding Source Files... dialogue box appears, make sure that the testbench is not selected for synthesis. Click OK
In the main ISE Project Navigator window Ensure that the "View" button has Simulation selected and the drop down list at the top left is set to "Behavioral".
Go to the "Hierarchy" pane and then right click and select "Manual Compile Order". Make sure exor2.vhd is above exor2tb.vhd

Part 1:

Modify the testbench file to use a component (currently it uses direct instantiation). You need a component so that configuration will work as expected.
In a third file, write a configuration for the test bench.
Select menu Project>Add Source... and select the new configuration file and click Open. Set the Association to Simulation and click OK.
Enter the name of the new configuration in the Top Module: box. Make sure the configuration file is selected in the "Hierarchy" pane.
In the Processes pane, double-click Simulate Behavioral Model. Inspect the waveforms and check that they are as expected. Close the simulation window.

Part 2:

Create a new VHDL library : Project>New VHDL Library... Enter the library name and location (eg ex02\ex02proj\isim). Click OK.
Move the EXOR2 gate to a new library: in the "Hierarchy" pane, right click on exor2.vhd and select "Source Properties...". In the "Source Properties - Design View Properties" dialog, select the new library in the "Source Library" drop-down menu. Click OK. Click OK.
In the same file as the previous configuration, write a new configuration for the test bench to use the exclusive or gate from the new library.
Enter the name of this new configuration in the Top Module: box. Make sure the configuration file is selected in the "Hierarchy" pane.
In the Processes pane, double-click Simulate Behavioral Model. Inspect the waveforms and check that they are as expected. Close the simulation window.

Part 3:

Write a second architecture for the exclusive or gate using four concurrent signal assignments, each of which describes a two-input nand function, and connecting them as shown in the circuit diagram in the workbook. Choose a meaningful name for the new architecture. Include the new architecture in the same file as the original entity and architecture for the exclusive or gate (as shown in the workbook).
In the same file as the previous configurations, write a new configuration for the test bench to use the second architecture of the exclusive or gate.
Enter the name of this new configuration in the Top Module: box. Make sure the configuration file is selected in the "Hierarchy" pane.
In the Processes pane, double-click Simulate Behavioral Model. Inspect the waveforms and check that they are as expected. You might like to temporarily modify the design in some way in order to check that the correct architecture has been simulated. Close the simulation window.

Part 4:

Enter the name of the test bench entity in the Top Module: box. Make sure the testbench file is selected in the "Hierarchy" pane.
Add appropriate statement(s) to the test bench entity context clause, so that the exclusive or entity will be picked up automatically.
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected.

Part 5:

Write a second architecture for the test bench containing two instances of the exclusive or gate component side-by-side and some logic to compare the outputs to make sure they are the same. (For example, you could exclusive or the outputs together using a concurrent signal assignment.) Include the new test bench architecture in the same file as the original test bench.
In the same file as the previous configurations, write a new configuration for the test bench that uses a different architecture for each of the two instances of the exclusive or gate.
Enter the name of this new configuration in the Top Module: box. Make sure the configuration file is selected in the "Hierarchy" pane.
In the Processes pane, double-click Simulate Behavioral Model. Inspect the waveforms and check that they are as expected. Close the simulation window.

ModelSim

These instructions assume you are following the instructions in the workbook. This section gives the ModelSim commands to carry out the various instructions in the workbook.

Set up:

Start ModelSim.
File > Change Directory to the ex02 directory.

Part 1:

In the ModelSim Transcript window, create a new VHDL library and make it the working library.

vlib part1
vmap work part1

Compile the exor gate design into that library.

vcom exor2.vhd

Modify the test bench file to use a component (currently it uses direct instantiation). You need a component so that configuration will work as expected.
Compile the test bench.

vcom exor2tb.vhd

In a third file (exor2cf.vhd), write a configuration (exorcf_part1) for the test bench.
Compile the configuration.

vcom exor2cf.vhd

Load the configuration into the simulator (vsim <configuration design unit name>). For example:
```
vsim exorcf_part1 -voptargs=+acc
```
Add the top-level test bench signals to the Wave window, run the simulation, and check that the simulation results are correct.

add wave /*
run -all
wave zoom full

Quit (unload) the simulation, but keep ModelSim open.

quit -sim

Part 2:

Remove the mapping to the work library (done in Part 1) in case you desire to remap library work to a new VHDL library.

vmap -del work

Create two new libraries.

vlib LIB1
vlib TB_LIB

Compile the exclusive or into the first library.

vcom exor2.vhd -work LIB1

Compile the test bench into the second library.

vcom exor2tb.vhd -work TB_LIB

In the same file as the previous configuration (exor2cf.vhd), write a new configuration (exorcf_part2) for the test bench to use the exclusive or gate from the new library (LIB1).
Compile and simulate the new configuration (exorcf_part2).

vcom exor2cf.vhd -work TB_LIB
vsim TB_LIB.exorcf_part2 -voptargs=+acc
add wave /*
run -all
wave zoom full

Quit (unload) the simulation, but keep ModelSim open.

quit -sim

Part 3:

Write a second architecture for the exclusive or gate using four concurrent signal assignments, each of which describes a two-input nand function, and connecting them as shown in the circuit diagram in the workbook. Choose a meaningful name for the new architecture. Include the new architecture in the same file (exor2.vhd) as the original entity and architecture for the exclusive or gate (as shown in the workbook).
Compile the exclusive or gate into the first library (LIB1).

vcom exor2.vhd -work LIB1

In the same file as the previous configurations (exor2cf.vhd), write a new configuration (exorcf_part3) for the test bench to use the second architecture of the exclusive or gate.
Compile and simulate the new configuration (exorcf_part3).

vcom exor2cf.vhd -work TB_LIB
vsim TB_LIB.exorcf_part3 -voptargs=+acc
add wave /*
run -all
wave zoom full

Check that the correct exclusive or architecture is being used by viewing the design hierarchy in the Structure (sim) window tab within ModelSim. Verify the design unit hierarchy is as expected from the Instance and Design Unit columns.
Quit (unload) the simulation, but keep ModelSim open.

quit -sim

Part 4:

Add appropriate statement(s) to the test bench entity's context clause, so that the exclusive or entity will be picked up automatically.
Compile and simulate the test bench. Do not use any configurations.

vcom exor2tb.vhd -work TB_LIB
vsim TB_LIB.exor2tb -voptargs=+acc
add wave /*
run -all
wave zoom full

Check that the correct exclusive or architecture is being used by viewing the design hierarchy in the Structure (sim) window tab within ModelSim.
Quit (unload) the simulation, but keep ModelSim open.

quit -sim

Part 5:

Write a second architecture for the test bench containing two instances of the exclusive or gate component side-by-side and some logic to compare the outputs to make sure they are the same. (For example, you could exclusive or the outputs together using a concurrent signal assignment.) Include the new test bench architecture in the same file (exor2tb.vhd) as the original test bench.
Compile the test bench.

vcom exor2tb.vhd -work TB_LIB

In the same file as the previous configurations, write a new configuration (exorcf_part5) for the test bench that uses a different architecture for each of the two instances of the exclusive or gate.
Compile and simulate the new configuration.

vcom exor2cf.vhd -work TB_LIB
vsim TB_LIB.exorcf_part5 -voptargs=+acc
add wave /*
run -all
wave zoom full

Inspect the simulation waveforms and verify they are as expected.
Check in the simulator that the correct architectures are being used (as shown in the workbook).
Quit (unload) the simulation and exit ModelSim.

quit -sim
exit -f

General Commands:

vlib <library name>	TO CREATE A LIBRARY
vmap work <library name>	TO MAP A LIBARY TO "work"
vcom <VHDL file>	TO COMPILE
vsim <configuration or top-level entity name>	TO ELABORATE AND INITIALIZE A SIMULATION
run -all	TO RUN A SIMULATION
restart -f	TO RESTART A SIMULATION

Vivado

These instructions assume you are starting a new project.

Set up:

Start Vivado and click on Create New Project
Next
Set project location to ... ex02, Project Name to "ex02proj", Next
RTL Project, Next
Add Sources - add ex02\exor2.vhd, ex02\exor2tb.vhd. Make sure that the testbench is not selected for synthesis. Next
Add Existing IP (optional), Next
Add Constraints (optional), Next
Click on Boards, Select the Zedboard, Next
Finish
Go to the "Sources" tab then the "Hierarchy" tab and then right click and select "Hierarchy Update" -> "Automatic Update, Manual Compile Order".

Part 1:

Modify the testbench file to use a component (currently it uses direct instantiation). You need a component so that configuration will work as expected.
In a third file, write a configuration for the test bench.
In the Flow Navigator, click "Add Sources". Click "Add or Create Simulation Sources". Next. Click "Add Files..." and select the new configuration file. OK. Finish.
Go to the "Sources" tab then the "Hierarchy" tab and then right click on the configuration in the "Simulation Sources" tree and select "Set as Top".
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected.

Part 2:

Move the EXOR2 gate to a new library as follows: go to the "Sources" tab then the "Hierarchy" tab and then right click on exor2.vhd in the "Simulation Sources" tree and select "Source Node Properties...".In the "Source File Properties" window, click "..." by "Library:" and enter a new library name in the dialog that appears.
In the same file as the previous configuration, write a new configuration for the test bench to use the exclusive or gate from the new library.
Go to the "Sources" tab then the "Hierarchy" tab and then right click on the new configuration in the "Simulation Sources" tree and select "Set as Top".
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected.

Part 3:

Write a second architecture for the exclusive or gate using four concurrent signal assignments, each of which describes a two-input nand function, and connecting them as shown in the circuit diagram in the workbook. Choose a meaningful name for the new architecture. Include the new architecture in the same file as the original entity and architecture for the exclusive or gate (as shown in the workbook).
In the same file as the previous configurations, write a new configuration for the test bench to use the second architecture of the exclusive or gate.
Go to the "Sources" tab then the "Hierarchy" tab and then right click on this new configuration in the "Simulation Sources" tree and select "Set as Top".
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected. You might like to temporarily modify the design in some way in order to check that the correct architecture has been simulated.

Part 4:

Go to the "Sources" tab then the "Hierarchy" tab and then right click on the testbench in the "Simulation Sources" tree (it will be under the last configuration simulated) and select "Set as Top".
Add appropriate statement(s) to the test bench entity context clause, so that the exclusive or entity will be picked up automatically.
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected.

Part 5:

Write a second architecture for the test bench containing two instances of the exclusive or gate component side-by-side and some logic to compare the outputs to make sure they are the same. (For example, you could exclusive or the outputs together using a concurrent signal assignment.) Include the new test bench architecture in the same file as the original test bench.
In the same file as the previous configurations, write a new configuration for the test bench that uses a different architecture for each of the two instances of the exclusive or gate.
Go to the "Sources" tab then the "Hierarchy" tab and then right click on this new configuration in the "Simulation Sources" tree and select "Set as Top".
In the Flow Navigator, click Run Simulation. In the dialog that appears, select Run Behavioral Simulation. Inspect the waveforms and check that they are as expected.