Simulating a Gate-Level Netlist (from Quartus) in ModelSim

  1. First test the RTL version using the given test bench.
    • Launch Modelsim and then set the working directory to:
    • ex06/simulate
      
    • Create a new working library.
    • Compile the counter and test bench files:
    •         ex06/source/counter.vhd
              ex06/source/counter_tb_pack.vhd
              ex06/source/counter_tb.vhd
              ex06/source/cfg_rtl.vhd
      
    • Simulate the configuration cfg_rtl. The tests pass if the OK signal remains true throughout.
  2. Now, to generate at gate-level netlist, follow the instructions in the README_Quartus HTML file.
  3. To simulate the gate-level netlist, you will need to compile the generated simulation model in ModelSim. This references libraries called
    altera
    and
    cycloneive.
    If you are using ModelSim Altera Edition, precompiled version of these libraries are provided and so you can miss out this step. If you are using any other version of ModelSim, you will need to compile these libraries yourself:
    • Create a new library called altera
    • Compile into this library the following source files, which you will find in the quartus/eda/sim_lib directory of the Quartus installation. If you are using a computer supplied by Doulos, Quartus is installed in C:/intelFPGA/ under Windows, or /apps/quartus under UNIX or Linux.
    • altera_primitives_components.vhd
      altera_primitives.vhd
      
    • Create another new library called cycloneive.
    • Compile into this library the following source files, which you will also find in the quartus/eda/sim_lib directory of the Quartus installation.
    • cycloneive_atoms.vhd
      cycloneive_components.vhd
      
  4. Compile the gate-level netlist into a new library:
    • Create a new library called
    • gate_lib
      
    • Compile the gate-level netlist into this library.
    • ex06/synthesize/simulation/modelsim/counter.vho
      
  5. Compile the gate-level configuration into the library you created for RTL simulation (not gate_lib):
  6. ../source/cfg_gate.vhd
    
  7. Next select the gate-level configuration and
    • Select menu Simulate > Start Simulation...
    • Expand the library containing the configuration and select the gate-level configuration (without clicking on OK):
    • ../source/cfg_gate.vhd
      
    • Change the resolution to ps.
    • Click on the SDF tab
    • Click on the "Add..." button and browse to find the SDF file, then click on "Open".
    • ex06/synthesize/simulation/modelsim/counter_vhd.sdo
      
    • You must now select a region. Type /uut.
    • Set the delay to max using the drop-down list.
    • Click on OK to close the Add SDF dialog.
    • Click on OK to close the Start Simulation dialog.

Run the simulation in the usual way. Take a careful look to the waveform and messages in the transcript window. You should see the outputs are delayed by real delays.