Synthesis and Place and Route

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Xilinx Vivado Synthesis and Place & Route

This section describes synthesis use Xilinx's Vivado synthesis tool, followed by Place & Route in Vivado. If you are using a third party synthesis tool (such as Synopsys Synplify, Mentor Precision), follow those instructions instead.

If you already have a project set up, jump to Vivado Synthesis

  1. Run Vivado - windows menu
    Xilinx Design Tools > Vivado NNNN.M > Vivado NNNN.M
  2. Create a project:
    • Click on Create New Project
    • Click Next
    • Name: ex01proj
    • Location: <this folder> i.e. ex01\implement\xilinx_zedboard
    • click Next
    • Select RTL Project, click Next
  3. To add the sources
    • Click "Add Files..."
    • Browse to ex01\source
    • Highlight logic.vhd, and click OK
    • Make sure Copy Sources into project is NOT checked
    • Click Next
  4. Add Constraints
    • Click "Add Files..."
    • Select "Files of type:" "Design Constraint Files (.sdc, .xdc)" in field at the bottom of the window
    • Browse to ex01\implement\xilinx_zedboard and highlight LOGIC.xdc
    • Click OK
    • Click Next
  5. To select the default part
    • Click on Boards at the top left of the form
    • Highlight Zedboard Zynq Evaluation and Development Kit in the list that appears
    • Click Next
  6. Finally click Finish to complete the project

Vivado Synthesis

  1. To synthesize the design using Vivado Synthesis:
    • In the Sources pane, make sure you can see LOGIC-RTL as a design source
    • Click on Run Synthesis in the Flow Navigator at the left

    After a while synthesis will complete and if a "Synthesis Completed" dialog appears, click Cancel. Now you can view the synthesized design, either as RTL, or mapped onto technology primitives.

  2. To view the RTL Design
    • In the Flow Navigator, expand the heading RTL Analysis
    • Click on Open Elaborated Design (and click OK if a dialog window appears)
    • The elaborated schematic will open. This is sometimes called the "RTL view or schematic" and shows a diagram of the logic
  3. To view the same circuit mapped to the technology library:
    • In the Flow Navigator, expand the heading Synthesis
    • Under Synthesis, expand the heading Open Synthesized Design
    • If prompted to close the elaboarated design, click Yes
    • Click on Schematic
    • You will see a view of the circuit drawn in Xilinx primitives

 

The next step is Place &Route. The tool will place and route the logic on the device, using the constraints specified in the file LOGIC.xdc. LOGIC.xdc specifies the pin locations so that the switches and LEDs on the Zedboard are used as we want.

  1. To view the constraint file
    • In the Sources pane, click the > next to Constraints
    • Double click on the file LOGIC.xdc
    • A file editor will open, showing you the Tcl (Tool Control Language) commands that set the pin locations and I/O voltage standards
    • Close the file
  2. The next step is to place and route the design.
    • In the Flow Navigator, click Run Implementation
    • A dilaog box may appear saying the synthesis is out-of-date. If so, click Yes.
    • After a while, if the Implementation Completed dialog box appears, select Generate Bitstream, and click OK
    • If the dialog box did NOT appear, then click on Generate Bitstream in the Flow Navigator (under Program and Debug).

 

When the Generate Bitstream has completed, the Bitstream Generation Completed dialog box shows. Select View Reports, and click OK

 

Click here for instructions to download the design.

 


Synthesis with Synopsys Synplify Pro

  1. Run synplify pro. On Windows use the start menu,
    on Linux type
    synplify_pro&
    Select the license for "All FPGAs". If a "tip" appears, click OK
  2. Create a project
    • File > New...
    • select Project File (Project)
    • Browse to this folder
    • Set the name to ex01
    • click OK
  3. Click Implementation Options... button and set
    Xilinx Zynq
    XC7Z020
    CLG484
    -1
    
    Click OK
  4. Click the button Add File...
    • Browse to logic.vhd
    • Click <-Add
    • Click OK
  5. Click Run
  6. to view the graphics, use menu HDL Analyst > RTL > Hierarchical View
    or for the Technology view HDL Analyst > Technology Hierarchal View
  7. The synthesized netlist is in rev_1\ex01.edf

 

Done!

 

You can quit the tool.

 

To Place and Route and download the design, go to Place and Route

 


Implementation with Xilinx Vivado (EDIF input from 3rd party synthesis tool)

  1. Run Vivado - windows menu
    Xilinx Design Tools > Vivado NNNN.M > Vivado NNNN.M
  2. Create a project:
    • Click on Create New Project
    • Click Next
    • Name: ex01proj
    • Location: <this folder> i.e. ex01\implement\xilinx_zedboard
    • click Next
    • Select Post-synthesis Project (leave the "Do not specify sources at this time" box unchecked)
    • click Next
  3. To add the sources
    • Click "Add Files..."
    • Browse to the EDIF file you generated in the synthesis step (eg rev_1/logic.edf)
    • Click OK
    • Make sure Copy Sources into project is NOT checked
    • Click Next
  4. Add Constraints
    • Click "Add Files..."
    • Select "Files of type:" "Design Constraint Files (.sdc, .xdc)" in field at the bottom of the window
    • Browse to ex01\implement\xilinx_zedboard and highlight LOGIC.xdc
    • Click OK
    • Click Next
  5. To select the default part
    • Click on Boards at the top left of the form
    • Highlight Zedboard Zynq Evaluation and Development Kit in the list that appears
    • Click Next
  6. Finally click Finish to complete the project
  7. To do place and route click Generate Bitstram in the Flow Navigator and click Yes in the dialog that appears
    After a while, a "Bitstream Generation Completed" dialog appears. Click Cancel.

 

Click here for instructions to download the design.

 


Downloading to the Zedboard (if a board is available)

  1. Make sure the board and JTAG USB cable are plugged in and switched on.
  2. In the Flow Navigator, click Open Hardware Manager

 

Now test if your downloaded design is working!

 


Testing the board

The 4 inputs are on slide/DIP switches SW0, SW1, SW2, SW3 at the bottom edge of the board. The 4 outputs are on the LEDs LD0, LD1, LD2, LD3. The pin numbers are printed on the board, so you can relate them back to the VHDL ports by looking in the LOGIC.xdc file.