Creating a RAM using the IP Catalog

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Generating a RAM

For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM.

  1. Run Intel Quartus Prime, either from the Windows Start Menu, or a desktop icon

    Linux
    quartus &
  2. To create a project:
    • You may be asked if you want to create a project - if so, click Yes
      Otherwise, select menu File > New Project Wizard...
    • If the New Project Wizard:Introduction appears, click Next
    • Set the following details:
      Working Directory   ex09/implement/intel_BeMicro/quartus
      Name of the project ex09proj
      Top Level Entity    ram1k8
      
      (The name of the project can be anything you like, but the Top Level Entity name must be ram1k8.)
    • Click Next
    • In the Project Type Page select "Empty project"
    • Click Next
    • In the Add Files page of the wizard, click on the small button in the right of the File name field - the button has three dots. Browse to ex09\source\ram1k8.vhd and click Open
    • Click Add... (this step is easy to forget!)
    • Click Next
    • In the Family & Device Settings page of the New Project Wizard:
      Family       Max 10
      Device       10M08DAF484C8GES
      
    • Click Finish
  3. Start the Intel Quartus Prime IP Catalog
    • Tools > IP Catalog and a window should open on the right of the main Quartus window
  4. Click on the small plus sign by "Basic Functions" and then "On Chip Memory"
    • Double click on "RAM: 1-PORT"
    • In the dialog that appears, set the IP variation file name to ex09\source\ram1k8mega.vhd by clicking on the elipsis ("...") button
    • and select IP variation file type : VHDL
    • Click OK
  5. After a short delay, a window "Megawizard Plug-In Manager [page 1 of 6]" appears (you might have to find it through Windows Explorer).
    • Set the ‘q’ output bus width to 8 bits
    • Set the number of 8 bit words to 1024
    • Leave the other options at their default values (Auto block type; single clock)
    • Click Next
  6. On to page 2...
    • Set the ‘q’ output so that it is not registered.
    • Click Finish
  7. The final "Summary" page will appear
    • Make sure the checkboxes with the Descriptions of Variation File, VHDL Component Declaration File, and Instantiation Template File are checked.
    • Click Finish
  8. A dialog window appears
    • Click Yes
  9. Have a look to see what has been generated in the ex09\source folder. The main files are ram1k8mega.vhd (the customised megafunction itself), ram1k8mega_inst.vhd (instantiation template), and ram1k8mega.cmp a component declaration example.
  10. You will now create a second RAM architecture that uses the generated block RAM.
    • Open the file source\ram1k8.vhd which has your original design.
    • Copy the first architecture then rename the copy. Delete all the existing code in the copy leaving only the architecture declaration, the word begin, and the end.
    • In the new architecture, create a component declaration of the megafunction. Copy the component declaration from ram1k8mega.cmp, and paste in front of the begin of your new architecture.
    • Using the example in the file ram1k8mega_inst.vhd, create a component instantiation of the generated RAM and connect it to the entity ports like this:
      ram1k8mega_inst : ram1k8mega port map (
        address => address,
        clock => clock,
        data => datain,
        wren => we,
        q => dataout
      );
      

Click here for instructions to modify the script and download the design.


Downloading the generated RAM to the Intel BeMicro Board

The VHDL is now complete - but how do the implementation tools know what to do? The implementation information is held in the file ex09\source\ram1k8mega.vhd. This file must be included in the script that compiles the design as follows:

  1. Edit the do_BeMicro.tcl script
    • Open the file ex09\implement\intel_BeMicro\do_BeMicro.tcl in an editor
    • Add this line to the script in front of the existing RAM model like this
      ../../../source/ram1k8mega.vhd
      ../../../source/ram1k8.vhd
      
  2. Just in case, delete any existing Quartus Prime project created from your first download by deleting the folder ex09\implement\intel_BeMicro\BeMicro
  3. To download the design
    • If necessary, open a command prompt by running ex09\implement\intel_BeMicro\openhere.bat
    • Run do_BeMicro.bat, watching carefully for any errors that might occur. You can open the project
      ex09\implement\intel_BeMicro\BeMicro\chip.qpf
      
      in Quartus Prime. If everything has worked, you should see an instance of M9K has been used to represent the RAM;; look in the Resource Section of the Fitter section of the Compilation Report.

You have completed the download of the generated ram using the MegaWizard!


(If you have time) Simulating the IP RAM

To simulate a design that contains a Megafunction instance, you will need to compile the generated Megafunction in ModelSim, that is the file ex09\source\ram1k8mega.vhd. You should also edit the testbench in ram_tb.vhd to select the second architecture of the RAM.

The Megafunction RAM model references a library altera_mf. If you are using ModelSim Altera Edition or Active-HDL, a precompiled version of that library is provided and you can proceed immediately to simulate the design.

If you are using another simulator, including any other version of ModelSim, you will need to compile the altera_mf library yourself, before attempting to compile ram1k8mega.vhd. Here are instructions for ModelSim; for a different simulator, you will need to adapt these accordingly:

  1. To compile altera_mf for Modelsim
    • In ModelSim, select menu File>New>Library...
    • Create a new library and a logical mapping to it called altera_mf – use the same name for the Library Name and the Library Physical Name.
    • Select menu Compile>Compile… and in the Compile Source Files dialogue, select Library: altera_mf from the drop-down list.
    • Browse to the directory in which the Intel Quartus Prime software is installed, and from there to the subdirectory quartus/eda/sim_lib.
    • Compile these two files (in this order):
      altera_mf_components.vhd
      altera_mf.vhd
      

You have now compiled the altera_mf library and, once you have compiled ram1k8mega.vhd and re-compiled ram1k8.vhd and ram_tb.vhd, you are ready to simulate the design. Make sure to set the simulation resolution to 1 ps in the Start Simulation dialogue.