Synthesis and Place and Route

Jump to...


Intel Quartus Prime Synthesis and Place & Route

This section describes synthesis use Intel's Quartus synthesis tool, followed by Place & Route in Quartus Prime. If you are using a third party synthesis tool (such as Synopsys Synplify, Mentor Precision), follow those instructions instead.

  1. Run Intel Quartus Prime, either from the Windows Start Menu, or a desktop icon

    Linux
    quartus &
  2. To create a project:
    • You may be asked if you want to create a project - if so, click Yes
      Otherwise, select menu File > New Project Wizard...
    • If the New Project Wizard:Introduction appears, click Next
    • Set the following details:
      Working Directory   browse to ex01\implement\intel_BeMicro\quartus
      Name of the project ex01proj
      Top Level Entity    LOGIC
      
      (The name of the project can be anything you like, but the Top Level Entity name must be LOGIC.)
    • Click Next
    • Click Next (Let the default option to Empty project)
    • In the Add Files page of the wizard, click on the small button in the right of the File name field - the button has three dots. Browse to ex01\source\logic.vhd and click Open
    • Click Next
    • In the Family & Device Settings page of the New Project Wizard:
      Family       Max 10
      Device       10M08DAF484C8GES
      
    • Click Finish
  3. We must now assign the pins to match those on the BeMicro board. There is a Tcl (Tool Control Language) script provided, which makes the appropriate pin assignments. To execute this script, you must first make sure that the Tcl console window is open. If it is not then
    • Select Menu View > Utility Windows > Tcl Console
    • In the Tcl Console window, type
        source ../BeMicro_pins.tcl
      
      You should see the messages
      "BeMicro Board - Pin assignment ..."
      "BeMicro Board - Pin assignment done!"
      
  4. Quartus Prime has a built-in VHDL synthesis tool. In Quartus Prime, the term "compile" is used to refer to the whole process of implementing a design, including synthesis and Place & Route.
    • Select menu Processing > Start Compilation
  5. When compilation has finished, you can view the synthesised design, either as an equivalent RTL circuit, or mapped onto technology primitives.
    • To view the RTL Design, select menu Tools > Netlist Viewers > RTL Viewer.
    • To view the same circuit mapped to FPGA resources, select menu Tools > Netlist Viewers > Technology Map Viewer (Post Mapping) and a different view of the same VHDL will appear, this time in technology elements of the Intel Max 10. The design should be mapped to three four-input lookup tables.

By clicking the Start Compilation button, you have carried out all the stages of Synthesis, Mapping, Fitting, and netlist generation. As part of this, Quartus Prime will have generated a bitstream with which to program the FPGA. You are now ready to download the bitstream to the board. You need to be using Microsoft Windows to do this.

Click here for instructions to download the design.


Synthesis with Synopsys Synplify Pro

  1. Run synplify pro. On Windows use the start menu,
    on Linux type
    synplify_pro&
    If a "tip" appears, click OK
  2. Create a project
    • File > New...
    • select Project File (Project)
    • Browse to this folder
    • Set the name to (for example) ex01
    • click OK
  3. Click Implementation Options... button and set
    Intel Max 10
    10M08DA
    F484C
    -8GES
    
    Click OK
  4. Click the button Add File...
    • Browse to logic.vhd
    • Click <-Add
    • Click OK
  5. Click Run
  6. To view the graphics, use menu HDL Analyst > RTL > Hierarchical View
    or for the Technology view HDL Analyst > Technology Hierarchal View
  7. The synthesized netlist is in rev_1\logic.vqm

Done!

You can quit the tool.

To Place and Route and download the design, go to Place and Route


Implementation with Quartus Prime (EDIF/VQM input from 3rd party synthesis tool)

This section describes synthesis using a third party tool (such as Synopsys Synplify, Mentor Precision) followed by followed by Place & Route in Quartus Prime.

  1. Run Intel Quartus Prime, either from the Windows Start Menu, or a desktop icon

    Linux
    quartus &
  2. To create a project:
    • You may be asked if you want to create a project - if so, click Yes
      Otherwise, select menu File > New Project Wizard...
    • If the New Project Wizard:Introduction appears, click Next
    • Set the following details:
      Working Directory   browse to ex01\implement\intel_BeMicro\quartus
      Name of the project ex01proj
      Top Level Entity    LOGIC
      
      (The name of the project can be anything you like, but the Top Level Entity name must be LOGIC.)
    • Click Next
    • In the Add Files page of the wizard, click on the small button in the right of the File name field - the button has three dots. Browse to ex01\implement\intel_BeMicro and find the netlist - for it may be called logic.vqm or logic.edf depending on the syntheis tool.
    • Click Open
    • Click Add... (this step is easy to forget!)
    • Click Next
    • In the Family & Device Settings page of the New Project Wizard:
      Family       Max 10
      Device       10M08DAF484C8GES
      
    • Click Finish
  3. We must now assign the pins to match those on the BeMicro board. There is a Tcl (Tool Control Language) script provided, which makes the appropriate pin assignments. To execute this script, you must first make sure that the Tcl console window is open.
    • Select Menu View > Utility Windows > Tcl Console
    • In the Tcl Console window, type
        source ../BeMicro_pins.tcl
      
      You should see the messages
      "BeMicro Board - Pin assignment ..."
      "BeMicro Board - Pin assignment done!"
      
  4. In Quartus Prime, the term "compile" is used to refer to the whole process of implementing a design, including synthesis and Place & Route.
    • Select menu Processing > Start Compilation
  5. When compilation has finished, you can view the synthesised design, either as an equivalent RTL circuit, or mapped onto technology primitives.
    • To view the RTL Design, select menu Tools > Netlist Viewers > RTL Viewer.
    • To view the same circuit mapped to FPGA resources, select menu Tools > Netlist Viewers > Technology Map Viewer and a different view of the same VHDL will appear, this time in technology elements of the Intel Max 10. The design should be mapped to three four-input lookup tables.

By clicking the Start Compilation button, you have carried out all the stages of Mapping, Fitting, and netlist generation. As part of this, Quartus Prime will have generated a bitstream with which to program the FPGA. You are now ready to download the bitstream to the board. You need to be using Microsoft Windows to do this.

Click here for instructions to download the design.


Downloading to the BeMicro Board

  1. Make sure the BeMicro board USB is connected and that the board is switched on.
  2. From Quartus Prime select menu Tools > Programmer.
  3. If nothing is listed under File, click on Add File ... button and select logic.sof from the output_files directory.
  4. Program the board by clicking on the Start button. (If the Start button is greyed out, please ask for assistance from the Course Leader - it is likely that the USB port needs connecting to the Virtual Machine on which you may be running). Once programmed you should see Successful in the Progress area.

Now test if your downloaded design is working!


Testing the board

The 4 inputs are on toggle/DIP switches of the Extension Board(S1). The 4 outputs are on the LEDs D1, D2, D3, D4 of the BeMicro Board. Note that these are all active low – when a switch is "on" it generates a "0". A "0" output lights the LED.

Given this, you should be able to work out which pin is connected to which LED by looking at the behaviour of the LEDs as you change the inputs!