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For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM.
quartus &
Working Directory ex09/implement/intel_BeMicro/quartus Name of the project ex09proj Top Level Entity ram1k8
Family Max 10 Device 10M08DAF484C8GES
ram1k8mega_inst : ram1k8mega port map ( address => address, clock => clock, data => datain, wren => we, q => dataout );
Click here for instructions to modify the script and download the design.
The VHDL is now complete - but how do the implementation tools know what to do? The implementation information is held in the file ex09\source\ram1k8mega.vhd. This file must be included in the script that compiles the design as follows:
../../../source/ram1k8mega.vhd ../../../source/ram1k8.vhd
ex09\implement\intel_BeMicro\BeMicro\chip.qpf
You have completed the download of the generated ram using the MegaWizard!
To simulate a design that contains a Megafunction instance, you will need to compile the generated Megafunction in ModelSim, that is the file ex09\source\ram1k8mega.vhd. You should also edit the testbench in ram_tb.vhd to select the second architecture of the RAM.
The Megafunction RAM model references a library altera_mf. If you are using ModelSim Altera Edition or Active-HDL, a precompiled version of that library is provided and you can proceed immediately to simulate the design.
If you are using another simulator, including any other version of ModelSim, you will need to compile the altera_mf library yourself, before attempting to compile ram1k8mega.vhd. Here are instructions for ModelSim; for a different simulator, you will need to adapt these accordingly:
altera_mf_components.vhd altera_mf.vhd
You have now compiled the altera_mf library and, once you have compiled ram1k8mega.vhd and re-compiled ram1k8.vhd and ram_tb.vhd, you are ready to simulate the design. Make sure to set the simulation resolution to 1 ps in the Start Simulation dialogue.