This file describes and Place & Route using Microsemi/Actel Libero which uses Synopsys Synplify or Mentor Precision as its synthesis tool, followed by Place & Route in Microsemi/Actel Designer.
First make sure you have carried out the instructions in the Advanced VHDL workbook, exercise 6 in the section "RTL Simulation".
Project Name ex06proj Location browse to ex06\synthesize Design Entry Type VHDL
Family: ProASIC3 Device: A3P250 Package: 208 PQFP Speed: -2 Core Voltage: 1.5 Range: COM
Default I/O Technology: LVTTL
For instructions to simulate the gate-level netlist, please refer to the relevant README file in the simulate directory.