Advanced VHDL ex06 - Quartus Prime Synthesis and Place & Route

This file describes and Place & Route using Intel Quartus Prime.

These instructions assume you are starting a new project.

  1. Run Intel Quartus Prime, either from the Windows Start Menu, or a desktop icon

    Linux
    quartus &
  2. To create a project:
    • You may be asked if you want to create a project - if so, click Yes
      Otherwise, select menu File > New Project Wizard...
    • If the New Project Wizard:Introduction appears, click Next
    • Set the following details:
      Working Directory   browse to ex06\synthesize
      Name of the project ex06proj
      Top Level Entity    Counter
      
      (The name of the project can be anything you like, but the Top Level Entity name must be Counter.)
    • Click Next
    • Click Next (Let the default option to Empty project)
    • In the Add Files page of the wizard, click on the small button in the right of the File name field - the button has three dots. Browse to ex06\source\counter.vhd and click Open
    • Click Next
    • In the Family & Device Settings page of the New Project Wizard:
      Family       Cyclone IV E
      Device       EP4CE6E22A7 (first of the list)
      
    • Click Next
    • In the EDA Tool Settings page, under Simulation, select the simulator you are using from the drop-down list.
    • Make sure the format is set to VHDL, and that the option to Run Gate Level Simulation automatically after compilation is NOT selected.
    • Click Finish
  3. Setup the project to use TimeQuest:
    • Select menu Assignments> Settings...
    • On the left, select the sub-category TimeQuest Timing Analyzer
    • Type counter.sdc as the SDC filename and click Add.
    • Click OK
  4. Synthesize the counter using Quartus Prime’s built-in VHDL synthesis tool:
    • Double-click Analysis & Synthesis in the Tasks pane on the left of Quartus Prime’s main window.
  5. Next, use TimeQuest to create the SDC (timing constraints) file:
    • Select menu Tools>TimeQuest Timing Analyzer (or click the toolbar icon – it looks like a blue clock.)
    • Select menu Netlist>Create Timing Netlist...
    • In the Create Timing Netlist dialog, select Post-map as the Input netlist and click OK.
  6. You will now enter a clock constraint.
    • Select menu Constraints>Create Clock… to open the Create Clock dialog.
    • You can leave the Clock name field blank.
    • Enter a Period of 10ns
    • Click the button with three dots that is to the right of the Target field.
    • In the Name Finder, with Collection set to get_ports, and Filter: *, click on List.
    • Double-click on "Clock" (or click once and then click on the ">").
    • You should see the clock as the only selected name. Click OK.
    • Click Run in the Create Clock dialog.
  7. At this point you might add more constraints, including ones for I/O timing. For simplicity, we will not be doing that.
  8. Now save the SDC file that you have created:
    • Select menu Constraints>Write SDC File… and type counter.sdc (the same file name you entered earlier).
    • Exit from TimeQuest
  9. In Quartus Prime, "compile" is used to refer to the whole process of implementing a design, including synthesis and place & route.
    • Click the Start Compilation button.
    • When Compilation has completed, click OK.
  10. Find the worst-case clock frequency and clock-output delay. Later, you will compare these with the simulation.
    • In the “Table of Contents”, expand "TimeQuest Timing Analyzer", expand "slow 1200mV 85C Model" and click on Fmax Summary and note the value in the Fmax field.
  11. You should find the SDF and VHDL gate level netlist files that Quartus Prime has written in a sub-directory of the project directory (ex06/synthesize) called simulation/Simulator-name, where Simulator-name is the name of the simulator you selected when setting up the project. Quartus Prime uses the following names for the netlist and SDF files:
    counter.vho     – Output VHDL gate level netlist
    counter_vhd.sdo – SDF file
    

For instructions to simulate the gate-level netlist, please refer to the relevant README file in the ex06 directory.