Timing Constraints and Timing Analysis

Jump to...


Setting Timing Constraints

Setting accurate timing constraints is an important part of the design flow. You will now set up some global constraints and analyze the results.

  1. Set up a project:
    • Start the ISE Project Navigator and create a new project called "counter" in the ex07\implemement\xilinx_spartan3E directory. Add your version of counter.vhd.
    • In the Processes windows, expand User Constraints
    • Double-click Create Timing Constraints
    • When prompted to create and add an Implementation Constraints File (UCF), click Yes.
  2. The Xilinx Constraints Editor opens. This is a graphical tool for entering timing constraints, which it writes to a UCF file.
    • In the "Constraint type" pane, ensure "Clock Domains" is highlighted
    • Double-click on the entry called "clock" in the "Unconstrained Clocks" list. This will bring up a dialog box where you can add many details of the clock timing. In this exercise we will add only the clock period:

      In the "Clock Signal Definition" section of the dialog box, make sure the "specify time" radio button is selected and type 10 for Time and choose "ns" for the units. There is no need to change the initial edge or duty cycle.
    • Click OK to save this constraint, then save and close the Constraint editor.
  3. Next you can implement the design and look at the results
    • Implement the design
    • When Place & Route has finished, click on Timing Constraints under Design Overview from the Design Summary.

      For each timing constraint, this will tell you whether the constraint was met, the Worst Case Slack, and the Best Case Achievable. "Slack" is the difference between the requirement and the actual value. These are worst-case values for the implemented design, not estimates.
  4. To obtain more detail use the Static Timing Report (open it from the Design Summary), or use the Timing Analyzer tool. To start the Timing Analyzer:
    • In the Processes window, expand Implement Design, then Place & Route and finally Generate Post-Place & Route Static Timing.
    • Double-click Analyze Post-Place & Route Static Timing.

This shows a detailed timing report, showing the three longest paths for each constraint. You can navigate the timing report using the links on the left.

Now you can go on to download your design using the do_spartan3e.bat script provided, as in previous exercises.