Using compxlib to compile libraries

If you are using any other simulator, including non-Xilinx versions of ModelSim, you will need to compile the XilinxCoreLib library yourself. You should do this before compiling the generated RAM model. The easiest method is to use the Simulation Library Compilation Wizard:

  1. (Windows) From the Start menu, launch the Simulation Library Compilation Wizard. You will find this under Xilinx ISE Design Suite nn > ISE Design Tools > Tools.

    (Linux) Type the command: compxlibgui &
  2. Select the simulator you are using. The Wizard should find the tool. If not, Browse to locate the simulator.
  3. Click Next.
  4. Select the HDL: VHDL and click Next.
  5. We only need the Spartan3E library, so deselect the two "All" options at the top and select Spartan3E. Click Next.
  6. Uncheck "FPGA Designs(UNISIM)...", "Timing Simulation library [...] (SIMPRIM)", and "EDK Simulation Library" but leave "CORE Generator(XilinxCoreLib)..." selected. (This is purely to save time. For a real design, you might need all libraries.) Click Next.
  7. Leave the Output directory for Compiled Libraries at its default value
  8. Check the option "Map only to existing pre-compiled libraries). This saves time if the libraries already exist (which they should do on Doulos PCs)
  9. Click Launch Compile Process>. This starts the compilation of XilinxCoreLib.

When the process has completed you can check the transcript to see if there were any errors: if you experience any problems, make sure that (i) the correct simulator and location were set up (ii) the simulator itself is in the PATH.

You have now compiled the XilinxCoreLib library and are ready to simulate the design as follows.

Go back to simulatethe design