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Setting accurate timing constraints is an important part of the design flow. You will now set up some global constraints and analyze the results.
Project Name counter Location browse to ex07\implement\microsemi_A3PE_Eval_Board Design Entry Type VHDL Family ProASIC3 Die A3P250 Package 208 PQFP Add Files ex07\source\counter.vhd
SmartTime reopens with the Summary report showing. Here you can see the maximum frequency for Clock after the layout and routing has been done. The external setup and hold times are shown along with the maximum and minimum Clock to out times.