Creating a RAM using CoreGen

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Generating a RAM

For simple RAM models, it is possible to write code that synthesizes a RAM. For more complex RAMs, and to use advanced features, you can use an IP generator to create the RAM. You will generate the same RAM as above, but this time using the Xilinx CORE Generator tool.

  1. Start the Xilinx Core Generator
    • Start Menu > Programs > Xilinx ISE Design Suite N.N > ISE Design Tools > Tools > CORE Generator, or use the link on the desktop
  2. Set up a project:
    • Select File > New Project
    • Set the name as ram1k8core.cgp
    • Set the Save In: location as ...ex09/source/ram1k8core
    • Click Save
  3. A dialogue box will appear to set up the part details:
    • Make sure Part is selected and set Spartan3E, xc3s500E, FG320, -4
    • Click on Generation.
    • Set Design Entry to VHDL
    • Set Vendor to ISE
    • Preferred Simulation Model should be set to Behavioral
    • Click OK
  4. Select the required function:
    • Follow the tree Memories & Storage Elements > RAMs & ROMs and select Block Memory Generator
    • In the right hand pane, click the blue word "Customize and Generate"
  5. Set the required parameters:
    • Set Component Name to ram1k8cgen, click Next
    • Select Single Port RAM, Click Next
    • Set Write Width to 8
    • Set Write Depth to 1024
    • Make sure Write First is selected
    • Make sure Always Enabled is selected
    • Click Generate
  6. After a while a readme file pops up. Have a look to see what has been generated. The most important files are ram1k8cgen.ngc, ram1k8cgen.vhd, and ram1k8cgen.vho.
    • Click Close to close the Readme File dialogue.
    • Close Core Generator by selecting menu File > Exit
  7. You will now create a second RAM architecture that uses the generated block RAM.
    • Open the file source/ram1k8.vhd which has your original design.
    • Copy the first architecture then rename the copy. Delete all the existing code in the copy leaving only the architecture declaration, the word begin, and the end.
    • In the new architecture, create a component declaration of the coregen RAM. To do this you can copy the component declaration from the file source\ram1k8core\ram1k8cgen.vho and paste it in front of the begin of your new architecture.
    • Using the example in the file source\ram1k8core\ram1k8cgen.vho, create a component instantiation of the generated RAM and connect it to the entity ports like this:
      ram1k8cgen_inst : ram1k8cgen
      port map (
      clka => clock,
      dina => datain,
      addra => address,
      wea(0) => we,  -- note wea(0) !
      douta => dataout);
      

      Note that port wea is a 1 bit wide vector!

Click here for instructions to modify the script and download the design.


Downloading the generated RAM to the Spartan 3E Board

The VHDL is now complete - but how do the implementation tools know what to do? The implementation information is held in the file ex09\source\ram1k8core\ram1k8cgen.ngc – in a proprietary Xilinx format. This file could be placed in the Xilinx project directory. Alternatively the do_spartan3e.tcl script could be told where to find the ngc file.

  1. Edit the do_spartan3e.tcl script
    • Open the file ex09\implement\xilinx_spartan3e\do_spartan3e.tcl in an editor
    • Add this line to the script (or just uncomment the line that's there for you
      set source_directory     ../../../source/ram1k8core
  2. Just in case, delete the existing xilinx project created from your first download by deleting the folder ex09\implement\xilinx_spartan3E\spartan3E
  3. To download the design
    • If necessary, open a command prompt by running ex09\implement\xilinx_spartan3E\openhere.bat
    • Run do_spartan3e.bat, watching carefully for any errors that might occur. If something goes wrong, you can look at the reports
      spartan3e_top.syr       Synthesis Report
      spartan3e_top.bld       Translate report 
      spartan3e_top_map.mrp   Map report 
      spartan3e_top.par       Place & Route report
      

Alternatively, you can view the reports in ISE by loading the project file, ex09\implement\xilinx_spartan3e\spartan3e\spartan3e_top.ise.

You have completed the download of the generated ram using CoreGen!


(If you have time) Simulating the IP RAM

To simulate a design that contains a CORE Generator instance, you will need to compile the generated model in your simulator. In this exercise, that is the file

ex09\source\ram1k8core\ram1k8cgen.vhd

You should also edit the testbench in ram_tb.vhd to select the second architecture of the RAM and compile that.

The generated RAM model references a library called XilinxCoreLib. If you are using ModelSim XE, Aldec Active-HDL, or Xilinx ISIM, a precompiled version of that library is provided and so you can proceed immediately to simulate the design.

If you are using Modelsim on a Doulos PC, then the library is again already compiled, and you can simulate straight away - click here

Only follow the instructions here if none of the above applies!. If in doubt, ask your course leader!

  1. Make sure, you set the simulation resolution to 1 ps in ModelSim’s Start Simulation dialog. (This is the default in ModelSim XE; other versions of ModelSim have a default resolution of 1 ns.)
  2. Remember that for simulation you'll need to compile
    source\ram1k8core\ram1k8cgen.vhd
    as well as source\ram1k8.vhd, and also make a library mapping to your compiled XilinxCoreLib - ask your course leader if you need help.