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A picture of the substrate layout is at the bottom of this page. (there were actually several overlays showing the interconnections, but I don't know how to do that in HTML)

The substrate is 48x40 mm rectangular and 1.52 mm thick, fired, white alumina (Al2O3, 96%. It has 14 milled wells for 12 custom Asic chips and 2 Xilinx chips.

Components:

• 12 custom Asic, die
• 9 Xilinx components, die\\
• 29 chip capacitors

I/O Contacts:

• Inputs: 34 contact pads, 1.5x0.45 mm pad, 0.7 mm pitch \\
• Outputs: 208 contact pads, 1.5x0.1 mm pads, 0.2 mm pitch

Circuitry:

• Basemetal : I/O pads, IC die backside metal contact, and 2 high-speed clock lines.
• 1st metal: analog signal layer
• 2nd metal: power plane
• 3rd metal: digital signal layer
• 4th metal: ground plane

General Information:

• 950 connection
• Number of vias: 3624
• Via pad size: 0.072 mm
• Via laser drill size: 0.045 mm
• Minimum trace size: 0.048 mm
• Minimum trace spacing: 0.048 mm

This is a 5x enlarged scale model of the 32-channel prototype of the MVD FEE. The final implementation will service 256 channels. It is an MCM (Multi Chip Module), where bare die, or unpackaged chips, are mounted in wells in a ceramic substrate, with their contacts facing up. A layer of polyamide, a kapton-like material, is mounted over the top. A laser drills vias, or holes, through the polyamide to some of the contact points. Then a layer of metal contact lines is laid down by photolithographic means, and the next layer of polyamide is applied. The process is repeated 4 times. Finally, some external components are mounted onto the assembly.