Notes on the muTr Calibration VME system boards
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MJL,PLM - updated 8/25/00

Order of boards in crate (left to right):
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ArcNet - DAC - Driver #1 - - - Driver #8 - Glink
(ArcNet and Glink boards require 2 slots, others only one slot)

DAC board
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DAC's on all versions of this boards are +/- 2 lsb's or 1% accuracy
exterior trigger :
  trigger (leading edge) +3 volts, >= 100 ns
  jumper on board can disable or enable this input
enable 
  +3 volts
  if not connected does not effect trigger if from Glink input
  but must be on if triggering from exterior trigger (above)
switch block
  sets address of driver card to drive (only for PC parallel port mode)
delay pot
  sets trigger delay, 100 ns to ~10us
  counter-clockwise all the way is minimum delay
width pot
  sets width of output, now 12us
  gives full pulse height for <=10us only
  about 1us/(1/4-turn) with clockwise narrower width
3-pin molex output
  output pulse, single -,+,grnd (top to bottom)
  jumper block sets for 50 or 100 ohm termination
  delayed by (above) width pot delay
DAC monitor
  two-pin voltage monitor point, +,- (top to bottom)
parallel port
  for control via Labview PC parallel port
PC enable
  towards board (down) disables PC parallel port control
  up disables ArcNet & Glink control and enable parallel control

Driver (Amp) Board
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switch block (8-position)
  address of this driver board, use only one bit on
  e.g. switch #1 is address 1
parallel port
  for Labview PC parallel port control
switch
  down disables parallel port control
LED's
  shows which channels enables, 8 LED's, #1 at bottom
  also one separate LED indicating an overheat if on
two 10-pin Molex outputs (delayed)
  top channels 1-4 (#1 at top, etc.)
  bottem channels 5-8
  ground on top and bottom pins
  signals +,- (top to bottom) for each output
headers
  determine what signals are terminated on this driver board
  with front panel up, looking at component side of board
    top-left header = clear
    next down and to right = clock
    over to right underneath shift register = data
    near VME connectors = pulse
  on driver #8 (rightmost) all four jumpers should be in
    to terminate all lines
  on other drivers only data jumper should be in

ArcNet Board
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switch block (8-position)
  ArcNet address, now 0xfe (largest legal address)
  position-1 is lsb, off=1 and on=0 as indicated on labels on board
  e.g. switch #5 off, others on, is 0xef
reset switch
  resets ArcNet
reset LED
  flashes during reset
LED bank
  CSO - will be used for Glink reset
  D1-8 - data bits
  clear, clock, ddaq

Glink Board
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switch block
  sets mode bits to use
  now #5 (counting starting at 0) is set
    MB2=on, MB3=off is calibration mode
    MB5=pulse is calibration trigger pulse
    switches 1-8 correspond to "mode #" 0-7, where "mode #" is
    bit pattern from mode bits
    e.g. mb2 & 5 on = "mode 5" -> switch 6 on (only)
    any one of mb2,3,5 could be pulsed (but plan is to pulse mb5)
reset switch
  resets GLink
Glink input
  use receive
Trigger out (top BNC connector)
  for scope, TTL (NOT delayed, i.e. prompt wrt fiber signal)
  rising edge is trigger
  pulse width is independent of real pulse width
Trigger disable
  +TTL to disable
  no input gives no effect
LEDS (listed top to bottem)
  trig - flash on valid trigger
  disab - trig disable input (on=disable)
  lvl1 - level-1
  mb5 - mode bit 5
  len - latch enable (getting valid data), on when dav & link on
  dav - data valid
  link - link up
  err - error (not locked)
  (1/10 sec stretch on trig, disab and lvl1 LED's)
  with no fiber connected: error & dav on (rest off)
  with fiber & synced: link, dav, len on; error off

Fuses
  All boards have temperature sensitive fuses
  Glink board - 2 Amp fuse
  other boards - 1 Amp fuses