--------------------------------------------------------------------- Calibration system for PHENIX muTr cathode strips - MJL + PLM 1/10/00 ===================================================================== The calibration will be done by pulsing 4 anode wires in each chamber with a voltage of up to 10 volts. These anode wires, which are located at the outer edge of each plane in an inactive region, are 2 anode and 2 field wires which are not connected to high voltage. The voltage will be varied over a wide range in order to calibrate the charge to data relationship for each cathode strip. The system can be configured to pulse up to 8 anode planes at a time in any combination. In addition the system will provide a tag in the DAQ data stream that identifies the data packets as calibration data with a certain amplitude pulse applied to certain anode planes. Offline/backend software modules will analyze the produced calibration data to determine the calibration of each sample on each cathode strip. As for real data, four samples will be taken on each cathode for each trigger. Earlier tests of the anode-pulsing calibration method are documented in a note from Dave Lee and Melynda Brooks (??). ArcNet controller software will cause configuration information to be downloaded to both the pulser and tagger (FPGA). The PHENIX fast-timing and control system will be programmed to provide a fast trigger to the pulsing system and also a level-1 accept to initiate readout and tagging of the data. In addition, the CPA preamp enable can be used to disable any combination of cathode channels. The system will consist of three parts, 1) the calibration crate which supplies the pulses, 2) the tagging of the data packets and 3) the calibration analysis modules which analyze the calibration data. Calibration Crate ----------------- The calibration crate will be mounted in the rear of the "eyebrow" racks just outside the magnet in a VME crate. It will consist of eight output driver boards (giving a total of 64 channels of output), a DAC board that produces the voltage pulse, an ArcNet board that is used to configure the amplitude and which outputs are enabled and a Glink board which will accept a trigger signal from the fast-timing and control for the pulsing. Also a number of front panel LED's will give a visual indication of the status of the pulsing system. All inputs and outputs will be isolated using optical isolators and transformers. In the VME crate the J1 connectors will be used for power and the J2 connectors and buss for signals between boards. Outputs will be driven by AD8016 ARP 50 ohm drivers through a transformer onto 110 ohm shielded twisted pair cable. These cables will run into the magnet and attach to each anode plane where they will be terminated with a 100 ohm resister. These drivers will be enabled or disabled according to configuration information downloaded via ArcNet by the use of analog switches. When in the disabled mode the drivers will also be in a low power state. The pulse will be about 20 microseconds long and will repeat at a rate of up to 1 khz. To provide for easy initial testing the DAC card will include a parallel test port (for control from a PC) and an external trigger input. The reference voltage level will be set by an 8 bit DAC and 10 volt reference (AD7224LN & AD584JN). Configuration data will be downloaded through an ArcNet card which includes a PHENIX Generic ArcNet card using 8-bit shift registers. The Generic ArcNet card will use 11 output bits (9 for data and two for clocking) to multiplex a total of 72 bits into several shift registers. 64 bits will determine which of 64 output channels are enabled. 8 bits will set the DAC level. The timing of the output pulses will come from a PHENIX fast-timing and control input which will also provide a calibration enable bit. MB2=1 and MB3=0 will signify a calibration event. A variable delay is provided on the fast trigger in order to adjust the relative timing between the pulsing crate and the level-1 accept. An additional input will allow gating of the pulsing system by a TTL signal, e.g. if one wants to disable it during SCR power supply spikes. Tagging of the calibration data ------------------------------- The Altera FPGA on the muTR FEM controller will tag the FEM packets using the 8 user words and one flag word in each muTR FEM packet. The tagging will use the flag word to indicate it is a calibration packet, and will use the first 72 bits in the user words to indicate which anodes are being pulsed and at what amplitude. If 8 anode planes are pulsed at a rate of 1 khz we estimate a data rate of approximately 48 Mb/sec which is about 2.4% of the (2 Gb/sec??) DAQ bandwidth. The FPGA software will obtain the tagging information from a serial download over ArcNet. The ArcNet interface software will receive the data and store it in FPGA memory some time well before a level-1 accept is issued. Then, in response to a level-1 accept, the FPGA packet builder will pull the information out of memory and insert it into the tagging words in the packets. Analysis of the calibration data -------------------------------- A PHOOL analysis module will be written that analyzes calibration data packets. The module will accumulate data on all cathode planes and then will analyze the data for linearization constants and record the results in the PHENIX database. Specifications of Calibration Crate ----------------------------------- The crate is a standard 6U VME crate with +5V and +/-12V supplies. The backplane has both the J1 and J2 connectors. DC power is connected to the usual J1 pins. The J2 backplane is used for the calibration control signals, which are 12V CMOS tri-state. Therefore the TTL terminators must be removed from the J2 backplane. All devices driving these control signals will use optoisolators, such as the Toshiba TLP2200 tri-state 5 Mbaud CMOS device. The control signals are 9 bits of serial data, a clock line, a clear line, a pulse trigger line, and a disable line, for a total of 13 CMOS signals. The only other signal on the backplane is the RF pulse (100 Ohm impedance). These signals are distributed on J2 lines B1 through 17 as follows: B2 gnd. 3 RF pulse (100 Ohm) positive going square wave 4 serial select chan., driver card 8 (12V CMOS) (8 bits, msb first) 5 " " " " " 7 " " " 6 " " " " " 6 " " " 7 " " " " " 5 " " " 8 " " " " " 4 " " " 9 " " " " " 3 " " " 10 " " " " " 2 " " " 11 " " " " " 1 " " " 12 gnd. 14 clear (active low) " " 15 serial data clock (pos. edge) " " 16 dac amplitude data (msb first) " " " 17 pulse trigger (neg. edge) (12V CMOS) 18 external disable input " " (forces bus to tri-state, active low) 22 gnd. 31 gnd. There are four types of VME cards which perform as follows : 1. Arcnet VME board with generic arcnet daughterboard. Receives the serial data, clock and clear signals from arcnet. Sequence is to : a: issue a bus clear (high - low - high) sequence. b: set clock bus line low. c: set msb serial bus data for each pulse driver card (8) plus the serial dac data (1), total of 9 bus lines. d: set clock high then low. data is latched on the positive edge. e: repeat steps c-d for the next 7 bits of serial data. A total of eight bus cycles downloads any DAC voltage and channel selection. This board uses +5V (for TTL logic) and +/-12V (optoisolators). 2. Fiber optic (Glink) fast timing and controls VME board. Once the serial download via arcnet is complete, the calibration pulses are triggered via a coincidence of two fast signals from the fiber optic receiver plus a front panel (TTL) external enable. The fast signals are presumably a gate signal and the 10 MHZ clock. The output drives the pulse trigger bus line. This board uses +5 VDC (for PECL/TTL logic) and +/-12V (optoisolators). 3. DAC VME board. Receives the serial data from the arcnet board. Using a shift register, it constructs an 8 bit amplitude which the DAC converts to an analog level. When a trigger is received from the fiber optic board, an FET gate is enabled which presents the DAC signal to a 100 ohm driver circuit. The pulse amplitude range is 0 to 10V. This signal is placed on the RF output bus line. The pulse timing (delay after trigger) and width are adjustable via trimmer resistors. Only +/-12VDC power is used. The DAC board also has a PC parallel printer port interface through which all of it's functions can be exercised. An external input enables this function while simultaneously disabling the arcnet and fiber optic boards, using the disable bus line. This interface is also capable of downloading one pulse driver VME board. The RF pulse may also be triggered by a TTL signal applied to input BNC connector. Front panel outputs of the DAC board include the DAC output voltage (DC) after downloading and a sample RF output pulse (100 ohm) when a trigger is issued. 4. Pulse driver VME boards (8). Receive 8 bits of serial data which are used to enable 8 channels of 100 ohm pulse drivers (total of 64 channels). Their front panel transformer-coupled outputs are cabled to the anode wires in the muon tracking chambers. The driver boards serial input data line is switch selectable using a dip switch. An array of 8 LED's on the front panel indicate which of the 8 channels are enabled. Only +/-12VDC power is used.